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参数资料
| 型号： | ICS87016AYT |
| 元件分类： | 时钟及定时 |
| 英文描述： | 87016 SERIES, LOW SKEW CLOCK DRIVER, 16 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48 |
| 文件页数： | 2/16页 |
| 文件大小： | 229K |
| 代理商： | ICS87016AYT |
Integrated
Circuit
Systems, Inc.
87016AY
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 28, 2006
10
ICS87016
LOW SKEW, 1-TO-16
LVCMOS/LVTTL CLOCK GENERATOR
APPLICATION INFORMATION
R2
1K
V
CC
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
INPUTS:
CLK INPUT:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1k
Ω resistor can be tied from the CLK input to
ground.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
Ω resistor can be tied from
CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
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相关代理商/技术参数 |
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| ICS8701CY | 制造商:ICS 功能描述: |
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