参数资料
型号: ICS8731CY-01T
元件分类: 时钟及定时
英文描述: PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封装: 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
文件页数: 15/16页
文件大小: 531K
代理商: ICS8731CY-01T
8731CY-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 6, 2006
8
Integrated
Circuit
Systems, Inc.
ICS8731-01
LOW SKEW, 1-TO-11 DIFFERENTIAL-TO-3.3V LVPECL
CLOCK MULTIPLIER / ZERO DELAY BUFFER
FIGURE 3C.
HIPERCLOCKS REF_CLK/nREF_CLK INPUT
DRIVEN BY 3.3V LVPECL DRIVER
FIGURE 3B.
HIPERCLOCKS REF_CLK/nREF_CLK INPUT
DRIVEN BY 3.3V LVPECL DRIVER
FIGURE 3D.
HIPERCLOCKS REF_CLK/nREF_CLK INPUT
DRIVEN BY 3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The REF_CLK /nREF_CLK accepts LVDS, LVPECL,
LVHSTL, SSTL, HCSL and other differential signals. Both
V
SWING and VOH must meet the VPP and VCMR input require-
ments. Figures 3A to 3D show interface examples for the
HiPerClockS REF_CLK/nREF_CLK input driven by the most
common driver types. The input interfaces suggested here
FIGURE 3A.
HIPERCLOCKS REF_CLK/nREF_CLK INPUT
DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER
are examples only. Please consult with the vendor of the
driver component to confirm the driver termination require-
ments. For example in Figure 3A, the input termination ap-
plies for ICS HiPerClockS LVHSTL drivers. If you are using
an LVHSTL driver from another vendor, use their termina-
tion recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
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