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| 型号： | ICS8741004AGT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 8741004 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | 4 40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24 |
| 文件页数： | 13/19页 |
| 文件大小： | 1309K |
| 代理商： | ICS8741004AGT |
ICS8741004
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS JITTER ATTENUATOR
IDT / ICS PCI EXPRESS JITTER ATTENUATOR
3
ICS8741004AG REV. ANOVEMBER 1, 2007
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number
Name
Type
Description
1, 24
QA1, QA1
Output
Differential output pair. LVDS interface levels.
3, 22
VDDO
Power
Output supply pins.
4, 5
QA0, QA0
Output
Differential output pair. LVDS interface levels.
6
MR
Input
Pulldown
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Q[Ax:Bx] to go LOW and the inverted outputs
Q[Ax:Bx] to go HIGH. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
7
BW_SEL
Input
Pullup/
Pulldown
PLL Bandwidth input. LVCMOS/LVTTL interface levels. See Table 3B.
8
nc
Unused
No connect.
9VDDA
Power
Analog supply pin.
10
F_SELA
Input
Pulldown
Frequency select pins for QAx/QAx outputs.
LVCMOS/LVTTL interface levels. See Table 3C.
11
VDD
Power
Core supply pin.
12
OEA
Input
Pullup
Output enable for QAx pins. When HIGH, QAx/QAx outputs are enabled.
When LOW, the QAx/QAx outputs are in a high impedance state.
LVCMOS/LVTTL interface levels. See Table 3A.
13
CLK
Input
Pulldown
Non-inverting differential clock input.
14
CLK
Input
Pullup
Inverting differential clock input.
15, 16
GND
Power
Power supply ground.
17
OEB
Input
Pullup
Output enable for QBx pins. When HIGH, QBx/QBx outputs are enabled.
When LOW, the QBx/QBx outputs are in a high impedance state.
LVCMOS/LVTTL interface levels. See Table 3A.
18
F_SELB
Input
Pulldown
Frequency select pins for QBx/QBx outputs.
LVCMOS/LVTTL interface levels. See Table 3C.
19
IREF
Input
A fixed precision resistor (RREF = 475
) from this pin to ground provides a
reference current used for differential current-mode QB0/nQB0 clock outputs.
20, 21
QB0, QB0
Output
Differential output pair. HCSL interface levels.
23, 24
QB1, QB1
Output
Differential output pair. HCSL interface levels.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN Input Pulldown Resistor
51
k
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| ICS8741004BGILF | 功能描述:IC PCI EXPRSS/JITT ATTEN 24TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:HiPerClockS™, FemtoClock™, PCI Express® (PCIe) 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
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| ICS874208BKILF | 制造商:Integrated Device Technology Inc 功能描述:IC CLK BUFFER/DIVIDER 32VFQFN |
| ICS874208BKILFT | 制造商:Integrated Device Technology Inc 功能描述:IC CLK BUFFER/DIVIDER 32VFQFN |
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