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| 型号： | ICS8741004AGT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 8741004 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | 4 40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24 |
| 文件页数： | 3/19页 |
| 文件大小： | 1309K |
| 代理商： | ICS8741004AGT |
ICS8741004
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS JITTER ATTENUATOR
IDT / ICS PCI EXPRESS JITTER ATTENUATOR
11
ICS8741004AG REV. ANOVEMBER 1, 2007
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
R1
50
R2
50
1.8V
Zo = 50
Zo = 50
CLK
nCLK
3.3V
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
HiPerClockS
Input
R3
125
R4
125
R1
84
R2
84
3.3V
Zo = 50
Zo = 50
CLK
nCLK
3.3V
LVPECL
HiPerClockS
Input
HCSL
*R3
33
*R4
33
CLK
nCLK
2.5V
3.3V
Zo = 50
Zo = 50
HiPerClockS
Input
R1
50
R2
50
*Optional – R3 and R4 can be 0
CLK
nCLK
HiPerClockS
Input
LVPECL
3.3V
Zo = 50
Zo = 50
3.3V
R1
50
R2
50
R2
50
3.3V
R1
100
LVDS
CLK
nCLK
3.3V
Receiver
Zo = 50
Zo = 50
CLK
nCLK
HiPerClockS
SSTL
2.5V
Zo = 60
Zo = 60
2.5V
3.3V
R1
120
R2
120
R3
120
R4
120
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PDF描述 |
|---|---|
| ICS8741004BGILFT | 8741004 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| ICS8745AMI-21LF | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| ICS8745AMI-21LFT | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
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| ICS8745AMI-21T | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS8741004BGILF | 功能描述:IC PCI EXPRSS/JITT ATTEN 24TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:HiPerClockS™, FemtoClock™, PCI Express® (PCIe) 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| ICS8741004BGILFT | 功能描述:IC PCI EXPRSS/JITT ATTEN 24TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:HiPerClockS™, FemtoClock™, PCI Express® (PCIe) 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| ICS874208BKILF | 制造商:Integrated Device Technology Inc 功能描述:IC CLK BUFFER/DIVIDER 32VFQFN |
| ICS874208BKILFT | 制造商:Integrated Device Technology Inc 功能描述:IC CLK BUFFER/DIVIDER 32VFQFN |
| ICS87421AMILF | 功能描述:IC CLK GEN DIFF-LVDS 8-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
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