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| 型号： | ICS8741004BGILFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 8741004 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, TSSOP-24 |
| 文件页数： | 20/20页 |
| 文件大小： | 1988K |
| 代理商： | ICS8741004BGILFT |
ICS8741004I
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS JITTER ATTENUATOR
PRELIMINARY
IDT / ICS PCI EXPRESS JITTER ATTENUATOR
9
ICS8741004BGI REV. B SEPTEMBER 27, 2007
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The ICS8741004I
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA and VDDO
should be individually connected to the power supply plane
through vias, and 0.01F bypass capacitors should be used for
each pin. Figure 1 illustrates this for a generic VDD pin and also
shows that VDDA requires that an additional 10 resistor along with
a 10
F bypass capacitor be connected to the V
DDA pin.
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Figure 2. Single-Ended Signal Driving Differential Input
VDD
VDDA
3.3V
10
10F
.01F
V_REF
Single Ended Clock Input
VDD
CLK
nCLK
R1
1K
C1
0.1u
R2
1K
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