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| 型号： | ICS8741004BGILFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 8741004 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, TSSOP-24 |
| 文件页数： | 6/20页 |
| 文件大小： | 1988K |
| 代理商： | ICS8741004BGILFT |
ICS8741004I
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS JITTER ATTENUATOR
PRELIMINARY
IDT / ICS PCI EXPRESS JITTER ATTENUATOR
14
ICS8741004BGI REV. B SEPTEMBER 27, 2007
Schematic Example
Figure 7 shows an example of ICS8741004I application schematic.
In this example, the device is operated at VDD = VDDO = 3.3V. Two
examples of LVDS terminations and two examples of HCSL
terminations are shown in this schematic. The input is driven by a
3.3V LVPECL driver. The decoupling capacitors should be located
as close as possible to the power pin.
Figure 7. ICS8741004I Schematic Example
QA0
To Logic
Input
pins
TL4
Zo = 50
+
-
C5
.1uf
R1
100
VDDO=3.3V
VDD
C2
10uF
C1
0.1uF
OEB
C3
0.01u
To Logic
Input
pins
R3
50
Zo = 50 Ohm
Recommended for
PCI Express Add-In
Card
VDDO
R7
33
U1
ICS8741004I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
/QA1
QA1
VDDO
QA0
/QA0
MR
BW_SEL
nc
VDDA
F_SELA
VDD
OEA
CLK
/CLK
GND
OEB
F_SELB
IREF
/QB0
QB0
VDDO
QB1
/QB1
/QA0
R10
50
LVPECL Driv er
Logic Control Input Examples
RU2
Not Install
R6
33
QA0
/QA0
C4
0.1u
/QB0
R11
50
QB0
R9
50
F_SELA
Zo = 50 Ohm
Set Logic
Input to
'1'
(U1:22)
VDDO
/QB0
QA1
R12
50
R14
50
TL8
Zo = 50
/QB1
Alternate
LVDS
Termination
+
-
Zo = 50 Ohm
/QA1
BW_SEL
OEA
RD2
1K
RD1
Not Install
Recommended for PCI
Express Point-to-Point
Connection
QB0
nCLK
CLK
Zo = 50 Ohm
F_SELB
VDDO
VDD = 3.3V
Zo = 50 Ohm
VDD
Zo = 50 Ohm
R2
50
R13
50
TL9
Zo = 50
HCSL Termination
R8
50
C6
.1uf
+
-
Set Logic
Input to
'0'
(U1:3)
RU1
1K
QB1
R4
10
MR
TL6
Zo = 50
VDD=3.3V
R5
475
+
-
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相关代理商/技术参数 |
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| ICS874208BKILF | 制造商:Integrated Device Technology Inc 功能描述:IC CLK BUFFER/DIVIDER 32VFQFN |
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