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| 型号： | ICS9148F-14 |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 13/18页 |
| 文件大小： | 807K |
| 代理商： | ICS9148F-14 |
4
ICS9148-14
Technical Pin Function Descriptions
VDD(1,2,3,4)
This is the power supply to the internal core logic of the
device as well as the clock output buffers for REF(0:3),
PCICLK,48/24MHzandSDRAM(0:7).
This pin operates at 3.3V volts. Clocks from the listed buffers
that it supplies will have a voltage swing from Ground to this
level. For the actual guaranteed high and low voltage levels
for the Clocks, please consult the DC parameter table in this
data sheet.
VDDL
This is the power supply for the CPUCLK output buffers.
The voltage level for these outputs may be 2.5 or 3.3volts.
Clocks from the buffers supplied by VDDL will have a voltage
swing from Ground to this level. For the actual Guaranteed
high and low voltage levels of these Clocks, please consult
the DC parameter table in this Data Sheet.
VDDH
This is the power supplies for the AGP output buffers. The
voltage level for these outputs is 3.3volts. Clocks from the
buffers supplied by VDDH will have a voltage swing from
Ground to this level. For the actual Guaranteed high and low
voltage levels of these Clocks, please consult the DC
parameter table in this Data Sheet.
GND (1, 2, 3, 4, H)
This is the power supply ground (common or negative) return
pin for the internal core logic and all the output buffers. See
Power Groups table for specific groupings.
X1
This input pin serves one of two functions. When the device
is used with a Crystal, X1 acts as the input pin for the
reference signal that comes from the discrete crystal. When
the device is driven by an external clock signal, X1 is the
device input pin for that reference clock. This pin also
implements an internal Crystal loading capacitor that is
connected to ground. See the data tables for the value of this
capacitor.
X2
This Output pin is used only when the device uses a Crystal
as the reference frequency source. In this mode of operation,
X2 is an output signal that drives (or excites) the discrete
Crystal. The X2 pin will also implement an internal Crystal
loading capacitor that is connected to ground. See the Data
Sheet for the value of this capacitor.
CPUCLK(0:2)
These Output pins are the Clock Outputs that drive processor
and other CPU related circuitry that requires clocks which are
in tight skew tolerance with the CPU clock. The voltage
swing of these Clocks are controlled by the Voltage level
applied to the VDDL pin of the device. See the Functionality
Table for a list of the specific frequencies that are available
for these Clocks and the selection codes to produce them.
AGP
This output pin is the clock that drives AGP or other related
circuitry. The voltage swing, of this clock is controlled by the
voltage level applied to the VDDH pin. This output frequency
is defined as 2X PCICLK, see frequency select table.
SDRAM(0:7)
These Output Clocks are use to drive Dynamic RAMs and
are low skew copies of the CPU Clocks. The voltage swing of
the SDRAMs output is controlled by the supply voltage
that is applied to VDD3 of the device, operates at 3.3 volts. In
Power Management Mode (MODE=0), the SDRAM clocks
are stopped low when both CPU_STOP# and PCI_STOP# are
low (see functionality table).
48/24MHz
This is a fixed frequency Clock output that is typically used
to drive Super I/O device. Defined as 24 or 48MHz by I2C
register (see table). See PWR_DWN# default definition, power
on default is at 48MHz.
REF(0:3)
The REF Outputs are fixed frequency Clocks that run at the
same frequency as the Input Reference Clock X1 or the
Crystal (typically 14.31818MHz) attached across X1 and X2.
PCICLK(0:4)
These Output Clocks generate all the PCI timing requirements
for a Pentium/Pro based system. They conform to the current
PCI specification. They run at default 33.3MHz at power_up
(see select table in I2C Byte0).
E_PCICLK
This output clock generates the PCI timing required for
docking stations and is early compared to the other PCI
clocks. It conforms to the current PCI specification and runs
at PCI frequency. It is controlled by PCI_STOP#.
FSEL
This Input pin controls the frequency of the Clocks at the
CPU,AGP, PCICLK and SDRAM output pins. If a logic 1
相关PDF资料 |
PDF描述 |
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| ICS9148F-14LF | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-14 | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-17-LF | 100.3569 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-17 | 100.3569 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-18LF | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9148F-17 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CPU System Clock Generator |
| ICS9148F-18 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148F-20 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148F25 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Industrial Control IC |
| ICS9148F-25 | 功能描述:IC CLK SYNTHESIZER CHIP 48-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
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