参数资料
型号: ICS9148F-17
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 100.3569 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封装: 0.300 INCH, SSOP-48
文件页数: 14/16页
文件大小: 473K
代理商: ICS9148F-17
7
ICS9148-17
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9148-17. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9148-17.
3. All other clocks except CPU and AGP clocks continue to run undisturbed.
相关PDF资料
PDF描述
ICS9148F-18LF 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
ICS9148F-25 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-32 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-58LF 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-58LF 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
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