参数资料
型号: ICS9148F-18LF
元件分类: 时钟产生/分配
英文描述: 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
封装: 0.209 INCH, SSOP-28
文件页数: 9/12页
文件大小: 285K
代理商: ICS9148F-18LF
6
ICS9148-18
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internally by the ICS9148-18 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The power on
latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are don’t care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
相关PDF资料
PDF描述
ICS9148F-25 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-32 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-58LF 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-58LF 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-58 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
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