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参数资料
| 型号： | ICS9148F-58LF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 2/14页 |
| 文件大小： | 449K |
| 代理商： | ICS9148F-58LF |
10
ICS9148- 58
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating
CL = 0 pF; 66.8 MHz
10
20
Supply Current
CL = 0 pF;133 MHz
20
40
TCPU-PCI
VT = 1.5 V; CPU leads
1
3
4
ns
TCPU-SDRAM VT = 1.5 V; Window
100
250
ps
1Guaranteed by design, not 100% tested in production.
Skew
1
IDD2.5OP
mA
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2VDD+0.3
V
Input Low Voltage
VIL
VSS-0.3
0.8
V
Input High Current
IIH
VIN = VDD
0.1
5
A
Input Low Current
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
2.0
A
Input Low Current
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
-100
A
Operating
CL = 0 pF; 66.8 MHz
100
160
Supply Current
CL = 0 pF; 133 MHz
200
320
Input frequency
Fi
VDD = 3.3 V;
12
14.318
16
MHz
CIN
Logic Inputs
5
pF
CINX
X1 & X2 pins
27
36
45
pF
Transition Time
1
Ttrans
To 1st crossing of target Freq.
3
ms
Settling Time
1
Ts
From 1st crossing to 1% target Freq.
2
ms
Clk Stabilization
1
TSTAB
From VDD = 3.3 V to 1% target Freq.
3
ms
TCPU-PCI
VT = 1.5 V; CPU leads
1
3
4
ns
TCPU-SDRAM VT = 1.5 V; Window
100
250
ps
1Guaranteed by design, not 100% tested in production.
IDD3.3OP
mA
Input Capacitance
1
Skew
1
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