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参数资料
| 型号： | ICS9148F-58LF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 7/14页 |
| 文件大小： | 449K |
| 代理商： | ICS9148F-58LF |
2
ICS9148- 58
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
VDD1
PWR
Ref (0:2), XTAL power supply, nominal 3.3V
2
REF0
OUT
14.318 MHz reference clock.
CPU3.3#_2.5
1,2
IN
Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V
CPU1. Latched input2
3,9,16,22,27,
33,39,45
GND
PWR
Ground
4X1
IN
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
5X2
OUT
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
6,14
VDD2
PWR
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
7
PCICLK_F
OUT
Free running PCI clock output. Synchrounous with CPUCLKs with 1-4ns
skew (CPU early) This is not affected by PCI_STOP#
FS1
1, 2
IN
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frequencies.
8
PCICLK0
OUT
PCI clock output. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
FS2
1, 2
IN
Frequency select pin. Latched Input Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frequencies.
10, 11, 12, 13
PCICLK(1:4)
OUT
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
15, 47
AGP (0:1)
OUT
Advanced Graphic Port outputs, powered by VDD4.
17
CPU_STOP#1
IN
This asyncheronous input halts CPUCLK (0:3) and AGP (0:1) clocks at
logic 0 level, when input low (in Mobile Mode, MODE=0)
SDRAM 11
OUT
SDRAM clock output. Frequency is selected by the SD_SEL latched input.
SD_SEL = 1 at power on causes SDRAM frequency = CPU frenquencies
SD_SEL = 0 at power on causes SDRAM frequencies = AGP frequencies
18
PCI_STOP#
1
IN
This asyncheronous input halts PCICLK(0:5) clocks at logic 0 level, when
input low (In mobile mode, MODE=0)
SDRAM 10
OUT
SDRAM clock output. Frequency is selected by the SD_SEL latched input.
SD_SEL = 1 at power on causes SDRAM frequency = CPU frenquencies
SD_SEL = 0 at power on causes SDRAM frequencies = AGP frequencies
20, 21,28, 29, 31,
32, 34, 35,37,38
SDRAM (0:9)
OUT
SDRAM clock outputs. Frequency is selected by the SD_SEL latched input.
SD_SEL = 1 at power on causes SDRAM frequency = CPU frenquencies
SD_SEL = 0 at power on causes SDRAM frequencies = AGP frequencies
19,30,36
VDD3
PWR
Supply for SDRAM (0:11), CPU Core and 24, 48MHz clocks,
nominal 3.3V.
23
SDATA
IN
Data input for I
2C serial input.
24
SCLK
IN
Clock input of I2C input
25
24MHz
OUT
24MHz output clock, for Super I/O timing.
MODE1, 2
IN
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
26
48MHz
OUT
48MHz output clock, for USB timing.
FS0
1, 2
IN
Frequency select pin. Latched Input Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frequencies.
40, 41, 43, 44
CPUCLK(0:3)
OUT
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
42
VDDL
PWR
Supply for CPU (0:3), either 2.5V or 3.3V nominal
46
REF1
OUT
14.318MHz reference clock.
SD_SEL
IN
Latched input at Power On selects either CPU (SDSEL=1) or AGP
(SD_SEL=0) frequencies for the SDRAM clock outputs.
48
VDD4
PWR
Supply for AGP (0:1)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9148F-60 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CPU System Clock Generator |
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| ICS9148F-PPP-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Mother Boards |
| ICS9148G-12 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148M-46 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CPU System Clock Generator |
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