参数资料
型号: ICS9148YF-111
元件分类: 时钟产生/分配
英文描述: 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封装: 0.300 INCH, SSOP-48
文件页数: 14/18页
文件大小: 545K
代理商: ICS9148YF-111
5
ICS9148-111
Third party brands and names are the property of their respective owners.
Bit
PWD
Bit6 Bit5 Bit4
CPU Clock
PCI
AGP
111
100
33.33
66.67
110
95.25
31.75
63.50
101
83.3
33.30
66.60
100
75
30.00
60.00
011
91.5
30.50
61.00
010
96.22
32.07
64.15
001
66.8
33.40
66.80
000
60
30.00
60.00
Description
Must be 0 for normal operation
0 -- +/- 0.25% Spread Spectrum Modulation
1 -- +/- 0.6% Spread Spectrum Modulation
Bit 7
Bit 3
Bit 2
0
Note 1
Bit 6:4
0 - Running
0 - Frequency is selected by hardware select, Latched inputs
1 - Frequency is selected by Bit 6:4 (above)
Must be 0 for normal operation
0 - Spread Spectrum center spread type.
Bit 1
Bit 0
1 - Tristate all outputs
0
1 - Spread Spectrum down spread type.
0 - Normal
1 - Spread Spectrum Enabled
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 000, and if
bit 3 is written to a 1 to use Bits 6:4, then these should be defined to desired frequency at same write cycle.
Note: PWD = Power-Up Default
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
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4
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4
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3
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Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
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