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参数资料
| 型号： | ICS9148YF-37LF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, LEAD FREE, MO-118, SSOP-48 |
| 文件页数： | 3/16页 |
| 文件大小： | 425K |
| 代理商： | ICS9148YF-37LF-T |
11
ICS9148-37
0143G—08/04/04
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating
IDD2.5OP
CL = 0 pF; 66.8 MHz
10
20
mA
Supply Current
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Lead
-500
200
500
ps
TCPU-PCI2
VT = 1.5 V; VTL = 1.25 V; CPU Leads
12.7
4
ns
1Guaranteed by design, not 100% tested in production.
Skew
1
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2VDD + 0.3
V
Input Low Voltage
VIL
VSS - 0.3
0.8
V
Input High Current
IIH
VIN = VDD
0.1
5
mA
Input Low Current
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
2.0
mA
Input Low Current
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
-100
mA
Operating
IDD3.3OP
CL = 0 pF; 66.8 MHz
100
160
mA
Supply Current
Input frequency
Fi
VDD = 3.3 V;
14.318
MHz
Input Capacitance
1
CIN
Logic Inputs
5
pF
CINX
X1 & X2 pins
27
36
45
pF
Transition Time
1
Ttrans
To 1st crossing of target Freq.
2
ms
Settling Time
1
Ts
From 1st crossing to 1% target Freq.
ms
Clk Stabilization
1
TSTAB
From VDD = 3.3 V to 1% target Freq.
2
ms
TCPU-SDRAM1 VT = 1.5 V; SDRAM Leads
-500
200
500
ps
TCPU-PCI1
VT = 1.5 V; CPU Leads
1
2.8
4
ns
TCPU-AGP
VT = 1.5 V; CPU Leads
-1
0
1
ns
1Guaranteed by design, not 100% tested in production.
Skew
1
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