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参数资料
| 型号： | ICS9148YF-37LF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, LEAD FREE, MO-118, SSOP-48 |
| 文件页数： | 7/16页 |
| 文件大小： | 425K |
| 代理商： | ICS9148YF-37LF-T |
15
ICS9148-37
0143G—08/04/04
General Layout Precautions:
1) Use a ground plane on the top
layer of the PCB in all areas not
used by traces.
2) Make all power traces and vias as
wide as possible to lower
inductance.
Notes:
1) All clock outputs should have
series terminating resistor. Not
shown in all places to improve
readibility of diagram.
2) 47 ohm / 56pf RC termination
should be used on all over 50MHz
outputs.
3) Optional crystal load capacitors
are recommended.
Connections toVDD:
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相关代理商/技术参数 |
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| ICS9148YF-46 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
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