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参数资料
| 型号： | ICS9222-01 |
| 英文描述： | Dual Memory Clock Generator |
| 中文描述： | 双内存时钟发生器 |
| 文件页数： | 2/6页 |
| 文件大小： | 97K |
| 代理商： | ICS9222-01 |
2
ICS9222-01
0274C—11/14/05
Pin Descriptions
Pin #
1, 7, 21, 22
2
3, 11
6, 8, 18, 25
Name
VDD
REFCLK
VDDC
GND
Type
PWR
IN
PWR
PWR
Description
3.3 V power supply
Reference clock
Power for phase aligners
Ground
Phase controller input, used to drive a phase aligner
that adjusts the phase of the busclk.
Voltage for phase detector inputs
Active low output enable/disable for CLK/CLKB
3.3V CMOS active low power down, the device is
powered down when the "(PD#) =0"
3.3V CMOS PLL Multiplier select, logic for selecting the
multiply ratio for the PLL from the input REFCLK
Clock output Complement
Clock output
3.3V CMOS Mode control, used in selecting bypass,
test, normal, and output test (OE)
4, 5, 9, 10
PCLK, SYNCLK
IN
12
13
VDDIPD
CLK_ STOP#
PWR
IN
14
PD#
IN
15, 16, 17
MULT (2:0)
IN
19, 24
20, 23
CLKB (1:0)
CLK (1:0)
OUT
OUT
26, 27, 28
FS (2:0)
IN
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