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参数资料
| 型号： | ICS9222-01 |
| 英文描述： | Dual Memory Clock Generator |
| 中文描述： | 双内存时钟发生器 |
| 文件页数： | 4/6页 |
| 文件大小： | 97K |
| 代理商： | ICS9222-01 |
4
ICS9222-01
0274C—11/14/05
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input / Supply / Outputs
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-10% (unless otherwise stated)
PARAMETER
SYMBOL
Supply Voltage
REFCLK Input cycle time
t
CYCLE,IN
Input Cycle-to-Cycle Jitter
Input Duty Cycle over 10K cycles
Input frequency of modulation
Modulation index
Phase detector input cycle time at PCLK (1:0) & SYNCLK (1:0)
t
CYCLE,PD
Initial phase error at phase detector inputs
Phase detector input duty cycle over 10K cycles
DC
IN,PD
Input rise & fall times (measured at 20%-80% of input voltage)
for PCLK (1:0), SYNCLK (1:0) & REFCLK
Input capacitance at PCLK (1:0) & SYNCLK (1:0) & REFCLK
Input capacitance matching at PCLK (1:0) & SYNCLK (1:0)
C
IN,PD
Input capacitance at CMOS pins
C
IN,CMOS
Input (CMOS) signal low voltage
Input (CMOS) signal high voltage
REFCLK input low voltage
REFCLK input high voltage
Input signal low voltage for PD inputs and STOP_CLK
Input signal high voltage for PD inputs and STOP_CLK
Input supply reference for REFCLK
Input supply reference for PD inputs
V
DD,IPD
Phase detector phase error for distributed loop measured at
PCLK (1:0) & SYNCLK (1:0)
t
ERR,PD
Clock Cycle time
Cycle-to-cycle jitter at CLK (1:0) & CLKB (1:0)
Total jitter over 2 ,3 or 4 cycles
Phase aligner phase step size CLK (1:0) & CLKB (1:0)
PLL output phase error when tracking SSC
t
ERR,SSC
Output crossing-point voltage
Output voltage during Clk Stop (CLK_STOP#=0)
V
X,STOP
Output Voltage swing
Output low voltage
Output high voltage
Output duty cycle over 10K cycles
Output cycle-to-cycle duty cycle error
t
DC,ERR
Output rise & fall times (measured at 20%-80% of input voltage)
for PCLK (1:0), SYNCLK (1:0) & REFCLK
t
CR
,t
CF
Difference between rise and fall times on a single device (20%-80%)
Operating Supply Current 400MHz
MIN
3.135
10
-
40%
30
0.25
30
-0.5
25%
MAX
3.465
40
250
60%
33
0.5
100
0.5
75%
UNIT
V
ns
ps
t
CYCLE
kHz
%
ns
t
CYCLE,PD
t
CYCLE,PD
V
DD
t
J,IN
DC
IN
F
M,IN
P
M,IN
t
err,init
t
IR
, t
IF
C
IN,PD
-
-
-
-
-
1
7
ns
pF
pF
pF
V
DD
V
DD
V
DD,IR
V
DD,IR
V
DD,IPD
V
DD,IPD
V
V
0.5
10
0.3
-
0.3
-
0.3
-
3.465
3.465
V
IL
V
IH
V
IL,R
V
IH,R
V
IL,R
V
IH,R
V
DD,IR
0.7
-
0.7
-
0.7
1.235
1.235
-100
2.5
-
-
1
-100
1.3
1.1
0.4
1
-
40%
-
100
3.75
60
100
-
100
1.8
2
1
-
2.35
60%
50
ps
ns
ps
ps
ps
ps
V
V
V
V
V
t
CYCLE
t
J
t
J
t
STEP
V
X
V
COS
V
OL
V
OH
DC
t
CYCLE
ps
300
-
500
100
250
ps
ps
mA
t
CR,CF
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