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参数资料
| 型号： | ICS9222YG-01LF-T |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9222 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 2 INVERTED OUTPUT(S), PDSO28 |
| 封装： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28 |
| 文件页数： | 2/6页 |
| 文件大小： | 93K |
| 代理商： | ICS9222YG-01LF-T |
2
ICS9222-01
0274C—11/14/05
Pin Descriptions
Pin #
Name
Type
Description
1, 7, 21, 22
VDD
PWR
3.3 V power supply
2
REFCLK
IN
Reference clock
3, 11
VDDC
PWR
Power for phase aligners
6, 8, 18, 25
GND
PWR
Ground
4, 5, 9, 10
PCLK, SYNCLK
IN
Phase controller input, used to drive a phase aligner
that adjusts the phase of the busclk.
12
VDDIPD
PWR
Voltage for phase detector inputs
13
CLK_ STOP#
IN
Active low output enable/disable for CLK/CLKB
14
PD#
IN
3.3V CMOS active low power down, the device is
powered down when the "(PD#) =0"
15, 16, 17
MULT (2:0)
IN
3.3V CMOS PLL Multiplier select, logic for selecting the
multiply ratio for the PLL from the input REFCLK
19, 24
CLKB (1:0)
OUT
Clock output Complement
20, 23
CLK (1:0)
OUT
Clock output
26, 27, 28
FS (2:0)
IN
3.3V CMOS Mode control, used in selecting bypass,
test, normal, and output test (OE)
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