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参数资料
| 型号： | ICS9248YF-110LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 115 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 13/14页 |
| 文件大小： | 152K |
| 代理商： | ICS9248YF-110LF |
8
ICS9248-110
Third party brands and names are the property of their respective owners.
Notes:
1. Default at power-up will be latched logic inputs to define frequency, as displayed by Bit 1.
2. PWD = Power-Up Default
Byte 6: SDRAM Clock & Generator Mode Control Register
Bit
PW D
7
0
90
30.0 0
60.00
0
1
95
31.6 7
63.33
0
1
0
100.99
33.6 6
67.33
0
1
115
38.3 3
76.67
0
1
0
100 .7
33.5 7
67.13
0
1
0
1
103
34.3 3
68.67
0
1
0
105
35.0 0
70.00
0
1
110
36.6 7
73.33
0
1
0
102
34.0 0
68.00
0
1
0
1
104
34.6 7
69.33
0
1
0
1
0
106
35.3 3
70.67
0
1
0
1
107
35.6 7
71.33
0
1
0
108
36.0 0
72.00
0
1
0
1
109
36.3 3
72.67
0
1
0
110
36.6 7
73.33
0
1
111
37.0 0
74.00
1
0
112
37.3 3
74.67
1
0
1
113
37.6 7
75.33
1
0
1
0
114
38.0 0
76.00
1
0
1
116
38.6 7
77.33
1
0
1
0
117
39.0 0
78.00
1
0
1
0
1
118
39.3 3
78.67
1
0
1
0
119
39.6 7
79.33
1
0
1
120
30.0 0
60.00
1
0
121
30.2 5
60.50
1
0
1
122
30.5 0
61.00
1
0
1
0
123
30.7 5
61.50
1
0
1
124
31.0 0
62.00
1
0
125
31.2 5
62.50
1
0
1
133.33
33.3 3
66.67
1
0
140
35.0 0
70.00
1
150
37.5 0
75.00
0
0 - SDRAM _OUT Disable
1 - SDRAM _OUT Enable
1
AGP
Reserved
Note1
1
0 - Frequen cy is selected by hardware select, latch ed input; Spread controlled b y pin 29
1 - Frequen cy is selected by Bit 6:2; Spread controlled by bit 7
0
Description
Spread Spectrum enable (+/- 0.25% cen ter spread) 1=ON 0=OFF
3,2, 6:4
B it 3
Bit 2
FS2
Bit 6
FS1
Bit 5
FS0
B it 4
CPU,
SDRAM
PCI
I
2C Command Bitmaps
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