参数资料
型号: ICS9248YF-110LF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 115 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封装: 0.300 INCH, SSOP-48
文件页数: 9/14页
文件大小: 152K
代理商: ICS9248YF-110LF
4
ICS9248-110
Third party brands and names are the property of their respective owners.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-110. It is used to turn off the PCICLK (0:5) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-110 internally. PCICLK (0:5) clocks are stopped in a low state and
started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off
latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-runningl)
CPU_STOP#
PWR_DWN#
PCICLK
(External)
PCI_STOP#
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