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参数资料
| 型号： | ICS9248YF-24 |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 22 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO56 |
| 封装： | 0.300 INCH, SSOP-56 |
| 文件页数： | 3/9页 |
| 文件大小： | 83K |
| 代理商： | ICS9248YF-24 |
3
ICS9250-24
0390C—11/06/02
Byte 0: Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PW
DN
O
I
T
P
I
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C
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D
7
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B6
1
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I
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A
(
0
K
L
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6
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B7
1
)
e
v
i
t
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I
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A
(
1
K
L
C
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P
5
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B0
11
)
e
v
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t
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I
/
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(
2
K
L
C
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C
P
4
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B1
11
)
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(
3
K
L
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P
3
t
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B4
11
)
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4
K
L
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P
2
t
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B5
11
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5
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1
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B7
11
)
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(
6
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C
P
0
t
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B8
11
)
e
v
i
t
c
a
n
I
/
t
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A
(
7
K
L
C
I
C
P
Byte 1: Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PW
DN
O
I
T
P
I
R
C
S
E
D
7
t
i
B1
21
)
e
v
i
t
c
a
n
I
/
t
c
A
(
8
K
L
C
I
C
P
6
t
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B2
21
)
e
v
i
t
c
a
n
I
/
t
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A
(
9
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L
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I
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P
5
t
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B4
21
)
e
v
i
t
c
a
n
I
/
t
c
A
(
0
1
K
L
C
I
C
P
4
t
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B5
21
)
e
v
i
t
c
a
n
I
/
t
c
A
(
1
K
L
C
I
C
P
3
t
i
B6
31
)
e
v
i
t
c
a
n
I
/
t
c
A
(
0
-
z
H
M
8
4
2
t
i
B7
31
)
e
v
i
t
c
a
n
I
/
t
c
A
(
1
-
z
H
M
8
4
1
t
i
B4
51
)
e
v
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t
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n
I
/
t
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A
(
0
-
z
H
M
4
1
0
t
i
B5
51
)
e
v
i
t
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I
/
t
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A
(
1
-
z
H
M
4
1
Notes:
1. Inactive means outputs are held LOW and are
disabled from switching.
2. DW - Default write values as in Intel Specification
stated.
T
I
B#
N
I
PW
DN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
d
e
v
r
e
s
e
R
6
t
i
B-
0
d
e
v
r
e
s
e
R
5
t
i
B-
0
d
e
v
r
e
s
e
R
4
t
i
B-
0
d
e
v
r
e
s
e
R
3
t
i
B-
0
d
e
v
r
e
s
e
R
2
t
i
B-
0
d
e
v
r
e
s
e
R
1
t
i
B-
0
d
e
v
r
e
s
e
R
0
t
i
B-
0
d
e
v
r
e
s
e
R
Byte 3: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PW
DN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
d
e
v
r
e
s
e
R
6
t
i
B-
0
d
e
v
r
e
s
e
R
5
t
i
B-
0
d
e
v
r
e
s
e
R
4
t
i
B-
0
d
e
v
r
e
s
e
R
3
t
i
B-
0
d
e
v
r
e
s
e
R
2
t
i
B-
0
d
e
v
r
e
s
e
R
1
t
i
B-
0
d
e
v
r
e
s
e
R
0
t
i
B-
0
d
e
v
r
e
s
e
R
Byte 4: Reserved, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PW
DN
O
I
T
P
I
R
C
S
E
D
7
t
i
B2
41
)
e
v
i
t
c
a
n
I
/
t
c
A
(
0
-
6
V
3
6
t
i
B3
41
)
e
v
i
t
c
a
n
I
/
t
c
A
(
1
-
6
V
3
5
t
i
B6
41
)
e
v
i
t
c
a
n
I
/
t
c
A
(
2
-
6
V
3
4
t
i
B7
41
)
e
v
i
t
c
a
n
I
/
t
c
A
(
3
-
6
V
3
t
i
B0
51
)
e
v
i
t
c
a
n
I
/
t
c
A
(
4
-
6
V
3
2
t
i
B1
51
)
e
v
i
t
c
a
n
I
/
t
c
A
(
5
-
6
V
3
1
t
i
B-
0
d
e
v
r
e
s
e
R
0
t
i
B-
0
d
e
v
r
e
s
e
R
T
I
B#
N
I
PW
DN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
d
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v
r
e
s
e
R
6
t
i
B-
0
d
e
v
r
e
s
e
R
5
t
i
B-
0
d
e
v
r
e
s
e
R
4
t
i
B-
0
d
e
v
r
e
s
e
R
3
t
i
B-
0
d
e
v
r
e
s
e
R
2
t
i
B-
0
d
e
v
r
e
s
e
R
1
t
i
B-
0
d
e
v
r
e
s
e
R
0
t
i
B-
0
d
e
v
r
e
s
e
R
Byte 5: ICS Reserved Register
(1= enable, 0 = disable)
Note: Don’t write into this register, writing into this
register can cause malfunction
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PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9248YF-39 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9248YF-64 | 制造商:ICS 制造商全称:ICS 功能描述:AMD-K7TM System Clock Chip |
| ICS9248YF-65 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENDIUM II Systems |
| ICS9248YF-66 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
| ICS9248YF-72 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
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