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参数资料
| 型号： | ICS9248YF-24 |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 22 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO56 |
| 封装： | 0.300 INCH, SSOP-56 |
| 文件页数： | 7/9页 |
| 文件大小： | 83K |
| 代理商： | ICS9248YF-24 |
7
ICS9250-24
0390C—11/06/02
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS.
The power down latency should be as short as possible but conforming to the sequence requirements shown below.
PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz
clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping
and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9250-24 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
3V66
PCICLK
VCO
Crystal
PD#
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| ICS9248YF-39 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
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| ICS9248YF-66 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
| ICS9248YF-72 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
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