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参数资料
| 型号： | ICS9248YF-72LF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200.01 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 5/12页 |
| 文件大小： | 552K |
| 代理商： | ICS9248YF-72LF |
2
ICS9248-72
Preliminary Product Preview
Pin Descriptions
Pin number
Pin name
Type
Description
1, 45, 46
IOAPIC[2:0]
Output
2.5V IOAPIC clock outputs
2
REF0
Output
3.3V, 14.318 MHz reference clock output.
3, 24, 29, 33
VDD
Power
3.3 V power
4
X1
Input
14.318 MHz crystal input
5
X2
Output
14.318 MHz crystal output
6, 14, 20, 26, 32
GND
Power
Ground
FS [2:1]
IN
Frequency select pins. Latched Inputs determins the CPU & PCI frequencies.
PCICLK [1:0]
Output
3.3 V PCI clock outputs, generating timing requirements for
9,17
VDDPCI
Power
3.3 V power for the PCI clock outputs
19, 18, 16, 15, 13,
12, 11, 10
PCICLK [9:2]
Output
3.3 V PCI clock outputs
23, 22, 21
3V66
Output
3.3 V 66 MHz clock output, fixed frequency clock typically used with AGP
25
SEL 133/100#
Input
control for the frequency of clocks at the CPU output pins. If logic "0" is used the
100 MHz frequency is selected. If Logic "1" is used, the 133 MHz frequency is
selected. The PCI clock is multiplexed to run at 33.3 MHz for both selected cases.
FS0
IN
Frequency select pin. Latched Inputs determins the CPU & PCI frequencies.
48 MHz
Output
3.3 V 48 MHz clock output, fixed frequency clock typically used with USB
devices
SEL24/48
IN
48/24 MHz select option. Active low = 48 MHz output. Active High = 24
MHz
24_48MHz#
Output
3.3V 48 or 24 MHz clock output, fixed frequency clock typically used with
USB devices.
30
SCLK
IN
Clock input of I2C input
31
PD#
Input
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped.
34
SDATA
IN
Data input for I
2C serial input.
36, 35
CPUCLK [1:0]
0utput
2.5 V CPU and Host clock outputs
37, 40
VDDLCPU
Power
2.5 V power for the CPU and Host clock outputs
41
GNDLCPU/2
Power
Ground for the CPU and Host clock outputs
42
CPU/2
Output
output running at 1/2 CPU clock frequency.Synchronous to the CPU outputs.
43
VDDLCPU/2
Power
2.5 V power for the CPU/2 clock outputs
47
GNDLIOAPIC
Power
Ground for IOAPIC clocks
48
GNDREF
Power
Ground for 14.318 MHz reference clock outputs
8, 7
28
27
Power Groups:
VDDREF,GNDREF=REF,X1,X2
GNDPCI,VDDPCI=PCICLK
VDD66,GND66=3V66
VDD48,GND48=48MHz
VDDCOR,GNDCOR=PLLCore
VDDLCPU/2,GNDLCPU/2=CPU/2
VDDLIOAPIC,GNDIOAPIC=IOAPIC
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9248YF-73-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9248YF-77 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
| ICS9248YF-78 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9248YF-80-T | 制造商:ICS 制造商全称:ICS 功能描述:General Purpose 133MHz System Clock |
| ICS9248YF-81 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers |
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