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参数资料
| 型号： | ICS9250YF-16-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 0.300 INCH, SSOP-56 |
| 文件页数： | 14/17页 |
| 文件大小： | 540K |
| 代理商： | ICS9250YF-16-T |
6
ICS9250-16
Byte 0: Control Register
(1 = enable, 0 = disable)
Byte 1: Control Register
(1 = enable, 0 = disable)
Byte 2: Control Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
These outputs are designed to be configured at power-on and are not
expected to be configured during the normal modes of operation.
2. PWD = Power on Default
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Notes:
1. Do not write in ID bits, these bits are for ICS internal use only.
2. Bit 0 will always read back 0. If readback/rewrite procedure is to
perform, user will need to ensure a "1" is written to Bit 0 for CPUCLK2
to maintain running status.
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相关代理商/技术参数 |
参数描述 |
|---|---|
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