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参数资料
| 型号： | ICS9250YF-18LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | ROHS COMPLIANT, SSOP-56 |
| 文件页数： | 13/16页 |
| 文件大小： | 311K |
| 代理商： | ICS9250YF-18LF |
6
ICS9250-18
Third party brands and names are the property of their respective owners.
0387C—09/08/05
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
d
e
v
r
e
s
e
R
6
t
i
B-
1
d
e
v
r
e
s
e
R
5
t
i
B-
1
d
e
v
r
e
s
e
R
4
t
i
B-
1
d
e
v
r
e
s
e
R
3
t
i
B6
41
)
t
c
a
n
I
/
t
c
A
(
F
_
M
A
R
D
S
2
t
i
B9
41
)
t
c
a
n
I
/
t
c
A
(
2
K
L
C
U
P
C
1
t
i
B1
51
)
t
c
a
n
I
/
t
c
A
(
1
K
L
C
U
P
C
0
t
i
B2
51
)
t
c
a
n
I
/
t
c
A
(
F
_
K
L
C
U
P
C
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
d
e
v
r
e
s
e
R
6
t
i
B8
1
)
t
c
a
n
I
/
t
c
A
(
F
K
L
C
I
C
P
5
t
i
B6
11
)
t
c
a
n
I
/
t
c
A
(
5
K
L
C
I
C
P
4
t
i
B4
11
)
t
c
a
n
I
/
t
c
A
(
4
K
L
C
I
C
P
3
t
i
B3
11
)
t
c
a
n
I
/
t
c
A
(
3
K
L
C
I
C
P
2
t
i
B2
11
)
t
c
a
n
I
/
t
c
A
(
2
K
L
C
I
C
P
1
t
i
B1
11
)
t
c
a
n
I
/
t
c
A
(
1
K
L
C
I
C
P
0
t
i
B9
1
)
t
c
a
n
I
/
t
c
A
(
0
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are
disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted
logic load of the input frequency select pin conditions.
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
X
#
0
S
F
d
e
h
c
t
a
L
6
t
i
B-
1
d
e
v
r
e
s
e
R
5
t
i
B-
1
d
e
v
r
e
s
e
R
4
t
i
B-
X
#
1
S
F
d
e
h
c
t
a
L
3
t
i
B-
1
d
e
v
r
e
s
e
R
2
t
i
B-
1
d
e
v
r
e
s
e
R
1
t
i
B-
X
#
3
S
F
d
e
h
c
t
a
L
0
t
i
B-
1
d
e
v
r
e
s
e
R
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
-
N
I
P
#
-
W
P
D
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
d
e
v
r
e
s
e
R
6
t
i
B-
X
#
2
S
F
d
e
h
c
t
a
L
5
t
i
B4
51
)
t
c
a
n
I
/
t
c
A
(
F
_
C
I
P
A
O
I
4
t
i
B5
51
)
t
c
a
n
I
/
t
c
A
(
0
C
I
P
A
O
I
3
t
i
B-
1
d
e
v
r
e
s
e
R
2
t
i
B-
1
d
e
v
r
e
s
e
R
1
t
i
B2
1
)
t
c
a
n
I
/
t
c
A
(
1
F
E
R
0
t
i
B3
1
)
t
c
a
n
I
/
t
c
A
(
0
F
E
R
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
d
e
v
r
e
s
e
R
6
t
i
B-
1
d
e
v
r
e
s
e
R
5
t
i
B9
21
)
t
c
a
n
I
/
t
c
A
(
z
H
M
8
4
t
i
B0
31
)
t
c
a
n
I
/
t
c
A
(
z
H
M
4
2
3
t
i
B
,
2
3
,
3
4
2
,
5
2
1)
t
c
a
n
I
/
t
c
A
(
)
5
1
:
2
1
(
M
A
R
D
S
2
t
i
B
,
1
2
,
2
8
1
,
9
1
1)
t
c
a
n
I
/
t
c
A
(
)
1
:
8
(
M
A
R
D
S
1
t
i
B
,
8
3
,
9
3
5
3
,
6
3
1)
t
c
a
n
I
/
t
c
A
(
)
7
:
4
(
M
A
R
D
S
0
t
i
B
,
3
4
,
4
0
4
,
1
4
1)
t
c
a
n
I
/
t
c
A
(
)
3
:
0
(
M
A
R
D
S
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9250YF-19 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9250YF-23 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9250YF-25-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9250YF-26-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9250YF-27-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
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