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| 型号： | ICS9250YF-37-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 144 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 0.300 INCH, SSOP-56 |
| 文件页数： | 1/12页 |
| 文件大小： | 343K |
| 代理商： | ICS9250YF-37-T |
Integrated
Circuit
Systems, Inc.
ICS9250-37
Third party brands and names are the property of their respective owners.
9250-37 Rev A 04/11/01
Preliminary Product Preview
Pin Configuration
56-Pin 300mil SSOP
Recommended Application:
Intel Tehema Chipset
Output Features:
4 Differential CPU Clock Pairs @ 3.3V
2 - 3V MREF clocks for memory reference seeds,
(separate single ended but 180 degrees out of phase)
4 - 66MHz reference output
10 - 3V 33MHz PCI clocks
2 - 48MHz clocks
2 - 14.318 reference output
Features:
Up to 156MHz frequency support
Support power management: Power Down Mode
Supports Spread Spectrum modulation: 0 to -0.5% down
spread and ±0.25 center spread.
Uses external 14.318MHz crystal
Select logic for Differential Swing Control, Test mode,
Tristate, Power down, Spread Spectrum, limited
frequency select, selective clock enable.
External resistor for current reference
Key Specifications:
3V66 Output jitter <300ps
CPU Output Jitter <200ps
MREF Output jitter <250ps
Frequency Generator for P4
GND
REF0
VDDREF
X1
X2
GNDREF
PCICLK0
PCICLK1
VDDPCI
PCICLK2
PCICLK3
GNDPCI
PCICLK4
PCICLK5
VDDPCI
PCICLK6
**FS2/PCICLK7
GNDPCI
**FS3/PCICLK8
SEL100_133#/PCICLK9
VDDPCI
SDATA
GND48
*
48MHz_0
**
48MHz_1
VDD48
PD#
MULTSEL0/
MULTSEL1/REF1
FS0/
FS1/
VDDMREF
3VMREF
3VMREF_B
GNDMREF
SCLK
CPUCLKT3
CPUCLKC3
VDDCPU
CPUCLKT2
CPUCLKC2
GNDCPU
CPUCLKT1
CPUCLKC1
VDDCPU
CPUCLKT0
CPUCLKC0
GNDCPU
I REF
VDDA
GNDA
VDD3V66
3V66-3
3V66-2
GND3V66
3V66-1
3V66-0
VDD3V66
ICS9250-37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
* This input has a 120K internal pull up to VDD.
** This input has a 120K internal pull down to GND.
PLL2
PLL1
Spread
Spectrum
48MHz (1:0)
3VMREF
PCICLK (9:0)
3VMREF_B
3V66 (3:0)
4
10
2
X1
X2
XTAL
OSC
CPU
DIVDER
3VMREF
DIVDER
PCI
DIVDER
3V66
DIVDER
PD#
MULTSEL (1:0)]
SEL100/133#
FS (3:0)
SCLK
SDATA
Control
Logic
Config.
Reg.
REF (1:0)
4
CPUCLKT (3:0)
CPUCLKC (3:0)
Block Diagram
Frequency Table
L
E
S
#
0
1
/
3
1
3
S
F2
S
F1
S
F0
S
FU
P
Cf
e
R
MI
C
P6
6
V
3
0
0000
0
.
0
90
0
.
5
40
0
.
0
30
0
.
0
6
0
000
1
0
.
0
10
0
.
0
53
3
.
3
37
6
.
6
00
0
1
0
4
.
0
10
2
.
0
57
4
.
3
33
9
.
6
00
0
1
0
.
3
0
10
5
.
1
53
3
.
4
37
6
.
8
6
00
1
0
.
5
0
10
5
.
2
50
0
.
5
30
0
.
0
7
00
1
0
1
0
.
8
0
10
0
.
4
50
0
.
6
30
0
.
2
7
00
1
0
.
0
1
10
0
.
5
57
6
.
6
33
3
.
3
7
0
111
0
.
2
1
10
0
.
6
53
3
.
7
37
6
.
4
7
0
1
000
0
.
5
1
10
5
.
7
53
3
.
8
37
6
.
6
7
1
000
1
3
.
3
17
6
.
6
63
3
.
3
37
6
.
6
10
0
1
0
6
.
3
10
8
.
6
60
4
.
3
30
8
.
6
10
0
1
0
.
6
3
10
0
.
8
60
0
.
4
30
0
.
8
6
10
1
0
.
8
3
10
0
.
9
60
5
.
4
30
0
.
9
6
10
1
0
1
0
.
0
4
10
0
.
0
70
0
.
5
30
0
.
0
7
10
1
0
.
2
4
10
0
.
1
70
5
.
5
30
0
.
1
7
1
0
111
0
.
4
10
0
.
2
70
0
.
6
30
0
.
2
7
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
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| ICS932S200BFLF | 功能描述:IC FREQ TIMING GENERATOR 56-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
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