参数资料
型号: ICS932S200
英文描述: Frequency Timing Generator for Dual Server/Workstation Systems
中文描述: 频率为双服务器/工作站系统时序发生器
文件页数: 2/12页
文件大小: 107K
代理商: ICS932S200
2
ICS932S200
0427C—07/03/02
Pin Descriptions
Pin number
1, 7, 8, 13, 19
20, 21, 24, 29,
38, 40, 44, 48,
52
3, 2
4,. 10, 16, 17,
22, 23, 27, 31,
39
5
6
9
18, 15, 14,
12, 11
Pin name
Type
Description
GND
PWR
Gnd pins
REF(1:0)
OUT
14.318MHz reference clock outputs at 3.3V
VDD
PWR
Power pins 3.3V
X1
X2
PCICLK_F
IN
OUT
OUT
XTAL_IN 14.318MHz crystal input
XTAL_OUT Crystal output
Free running PCI clock not affected by PCI_STOP#
PCICLK (4:0)
OUT
PCI clock outputs at 3.3V. Synchronous to CPU clocks.
26, 25
3V66 (1:0)
OUT
66MHz outputs at 3.3V. These outputs are stopped when CPU_STOP# is
driven active..
28
SEL 133/100#
IN
This selects the frequency for the CPU and CPU/2 outputs. High =
133MHz, Low=100MHz
Fixed 48MHz clock output. 3.3V
Function select pins. See truth table for details.
30
48MHz
SEL (1:0)
OUT
IN
33, 32
34
SPREAD#
IN
Enables spread spectrum when active(Low). modulates all the CPU, PCI,
IOAPIC and 3V66 clocks. Does not affect the REF and 48MHz clocks.
0.5% down spread modulation.
35
PD#
IN
This asynchronous input powers down the chip when drive active(Low).
The internal PLLs are disabled and all the output clocks are held at a Low
state.
This asychronous input halts the CPUCLK and the 3V66 clocks at logic "0"
when driven active(Low).
36
CPU_STOP#
IN
37
PCI_STOP#
IN
This asynchronous input halts the PCICLK at logic"0" when driven
active(Low). PCICLK_F is not affected by this input.
43, 47, 51, 56
50, 49, 46,
45, 42, 41
VDDL
PWR
Power pins 2.5V
Host bus clock output at 2.5V. 133MHz or 100MHz depending on the state
of the SEL 133/100MHz.
IOAPIC clocks at 2.5V. Synchronous with CPUCLKs but fixed at
16.67MHz.
CPUCLK (5:0)
OUT
55, 54, 53
IOAPIC (2:0)
OUT
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