参数资料
型号: ICS932S203AFLN
厂商: IDT, Integrated Device Technology Inc
文件页数: 13/18页
文件大小: 0K
描述: IC FREQ GEN W/CPU CLOCK 56-SSOP
标准包装: 26
类型: 时钟/频率发生器
PLL:
主要目的: Intel CPU 服务器
输入: 晶体
输出: 时钟
电路数: 1
比率 - 输入:输出: 1:23
差分 - 输入:输出: 无/是
频率 - 最大: 133.3MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 56-BSSOP(0.295",7.50mm 宽)
供应商设备封装: 56-SSOP
包装: 管件
其它名称: 932S203AFLN
IDTTM Frequency Generator with 133MHz Differential CPU Clocks
0601G—01/26/10
ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
4
Byte 0: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the
system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP
functionality via SMBus Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the SMBus Byte 0 Bit3. In Software mode it is not allowed to pull the
external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP
conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix
these modes.
In Hardware mode the SMBus byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in
PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (SMBus Byte 0 Bit 3 = 0)].
Byte 1: Control Register
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