参数资料
型号: ICS932S208DG
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封装: 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP
文件页数: 4/22页
文件大小: 231K
代理商: ICS932S208DG
12
Integrated
Circuit
Systems, Inc.
ICS932S208
0743D—07/07/04
I
2C Table: Read-Back Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
RESERVED
-
X
Bit 6
RESERVED
-
X
Bit 5
RESERVED
-
X
Bit 4
RESERVED
-
X
Bit 3
RESERVED
-
X
Bit 2
RESERVED
-
X
Bit 1
FSB
Freq Select 1 Read
Back
RX
Bit 0
FSA
Freq Select 0 Read
Back
RX
I
2C Table: Spreading and Device Behavior Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SRC/SRC#
SRC Free-Running
Control
RW
FREE-RUN
STOPPABLE
0
Bit 6
SRC
Output Control
RW
Disable
Enable
1
Bit 5
RESERVED
-
X
Bit 4
RESERVED
-
X
Bit 3
RESERVED
-
X
Bit 2
CPUT2/CPUC2
Output Control
RW
Disable
Enable
1
Bit 1
CPUT1/CPUC1
Output Control
RW
Disable
Enable
1
Bit 0
CPUT0/CPUC0
Output Enable
RW
Disable
Enable
1
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SRC_PD#
Drive Mode
0: Driven in PD#
RW
Driven
Hi-Z
0
Bit 6
SRC_Stop#
Drive Mode
0: Driven in
PCI_Stop#
RW
Driven
Hi-Z
0
Bit 5
CPUT2_PD# Drive
Mode
RW
Driven
Hi-Z
0
Bit 4
CPUT1_PD# Drive
Mode
RW
Driven
Hi-Z
0
Bit 3
CPUT0_PD# Drive
Mode
RW
Driven
Hi-Z
0
Bit 2
RESERVED
-
X
Bit 1
RESERVED
-
X
Bit 0
RESERVED
-
X
41, 40
-
47, 46
44, 43
38, 37
-
44, 43
41, 40
Byte 2
38, 37
-
Byte 0
-
RESERVED
-
RESERVED
-
RESERVED
0:driven in PD#
1: Tri-stated
-
RESERVED
READBACK of CPU(3:0)
Frequency
RESERVED
Byte 1
RESERVED
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