- 您现在的位置：买卖IC网 > PDF目录136444 > ICS932S208DG (INTEGRATED DEVICE TECHNOLOGY INC) 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 PDF资料下载
参数资料
| 型号： | ICS932S208DG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP |
| 文件页数： | 8/22页 |
| 文件大小： | 231K |
| 代理商： | ICS932S208DG |
16
Integrated
Circuit
Systems, Inc.
ICS932S208
0743D—07/07/04
PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power.
When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start
without glitches.
PD#, Power Down
#
N
W
D
R
W
PU
P
C#
U
P
CC
R
S#
C
R
S6
6
V
3I
C
P
/
F
I
C
PT
O
D
/
B
S
UF
E
Re
t
o
N
1l
a
m
r
o
Nl
a
m
r
o
Nl
a
m
r
o
Nl
a
m
r
o
Nz
H
M
6
6z
H
M
3
3z
H
M
8
4z
H
M
8
1
3
.
4
1
0r
o
2
*
f
e
r
I
t
a
o
l
F
t
a
o
l
F2
*
f
e
r
I
t
a
o
l
F
r
o
t
a
o
l
Fw
o
Lw
o
Lw
o
Lw
o
L
Notes:
1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation.
2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses.
PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be
held low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at
2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
PD# Assertion
相关PDF资料 |
PDF描述 |
|---|---|
| IDT79R3041-20JG | 32-BIT, 20 MHz, RISC PROCESSOR, PQCC84 |
| ICS950902DFLFT | 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| ICS843207CY-350 | 375 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| JT00RT-18-32PA(023) | 32 CONTACT(S), ALUMINUM ALLOY, MALE, MIL SERIES CONNECTOR, CRIMP, RECEPTACLE |
| JT00RT-18-32PB(023) | 32 CONTACT(S), ALUMINUM ALLOY, MALE, MIL SERIES CONNECTOR, CRIMP, RECEPTACLE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS932S208DGLF | 功能描述:IC TIMING HUB CTRL PROGR 56TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:TCH™ 标准包装:1 系列:- 类型:时钟/频率发生器，多路复用器 PLL:是 主要目的:存储器，RDRAM 输入:晶体 输出:LVCMOS 电路数:1 比率 - 输入:输出:1:2 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:Digi-Reel® 其它名称:296-6719-6 |
| ICS932S208DGLFT | 功能描述:IC TIMING HUB CTRL PROGR 56TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:TCH™ 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ICS932S208DGT | 功能描述:IC TIMING HUB CTRL PROGR 56TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:TCH™ 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ICS932S208YFLF-T | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor |
| ICS932S208YGLF-T | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor |
发布紧急采购，3分钟左右您将得到回复。