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参数资料
| 型号： | ICS9341YF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 2/9页 |
| 文件大小： | 207K |
| 代理商： | ICS9341YF |
2
ICS9341
Pin Descriptions
Pin number
Pin name
Type
D escription
1
G N D REF
PWR
G round pin for REF clocks.
2
X 1
IN
X TA L_IN 14.318M H z crystal input.
3
X 2
O UT
XTAL_OUT Crystal output.
4, 16
V D D PCI
PWR
3.3V olts pow er pin for PCICLK s.
5, 6, 7, 8, 17, 18,
19, 20
PCICLK (1:8)
O U T
PCI clock output at 3.3V . Synchronous to CPU clocks.
9, 24
G N D PCI
PWR
G round pin for PCI clocks.
10
G N D CPU B
PWR
G round pin for CPU B clocks.
11, 12, 13, 14
CPU B (1:4)
O U T
CPU CLK outputs up to 133.3M H z.
15
V D D CPU B
PWR
Pow er pin for the CPU bank B CLK s. 3.3V .
21, 22
FS (0:1)
IN
Logic - input for frequency selection.
23, 41
*O U T_SEL (0:1)
IN
These control the output functionality of the O U T and O U T/2 pins.
Refer to table for details.
24
G N D PCI
PWR
G nd pin for PCICLK s.
25
V D D A
PWR
Pow er for analog outputs.
26
*PCI_STO P#
IN
This active low input stops PCI clocks.
27, 28
N/C
-
Not connected
29
G N D D
PWR
D igitial ground
30
G N D A
PWR
A nalog ground
31
G N D O U T
PWR
G round for output pins.
32
OUT/2
O U T
H alf the O U T frequency. D ependent on O U T_SEL. Refer to table
for details.
33
OUT
O U T
This output frequency is dependent on O U T_SEL. Refer to table for
details.
34
V D D O U T
PWR
Pow er for O U T pins 3.3V .
35
V D D D
PWR
Pow er for digitial outputs.
36
CPU B_STO P#**
IN
This active low input stops the CPU B clocks at a logic "0" level
when input low .
45, 44, 38, 37
CPU A (1:4)
O U T
CPU CLK outputs up to 133.3M H z.
39
V D D CPU A
PWR
Pow er pin for the CPU bank A CLK s. 3.3V .
40
PD #
IN
This asynchronous input pow ers dow n the chip w hen drive
active(Low ). The internal PLLs are disabled and all the output clocks
are held at a Low state.
42
G N D CPU A
PWR
G round pin for CPU B clocks.
43
SS_EN
IN
Spread spectrum is turned on by driving this input high and turned
off by driving low .
46
V D D REF
PWR
Pow er pin for REF clocks.
47, 48
REF
O U T
14.318M H z reference clock outputs at 3.3V .
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9342 | 制造商:ICS 制造商全称:ICS 功能描述:133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS9342AFLF | 制造商:Integrated Device Technology Inc 功能描述: |
| ICS9342YF-T | 制造商:ICS 制造商全称:ICS 功能描述:133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS93701 | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
| ICS93701YGT | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
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