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参数资料
| 型号： | ICS93V847YG-T |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | 0.173 INCH, MO-153, TSSOP-24 |
| 文件页数： | 2/9页 |
| 文件大小： | 66K |
| 代理商： | ICS93V847YG-T |
2
ICS93V847
0611C—06/18/03
Pin Descriptions
This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels.
ICS93V847 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to five differential
pair of clock outputs (CLKT(4:0), CLKC(4:0)) and one differential pair feedback clock output (FB_OUT, FB_OUTC).The
clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC) and the
Analog Power input (AVDD). When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
The PLL in ICS93V847 clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT(4:0), CLKC(4:0)). ICS93V847
is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS93V847 is characterized for operation from 0°C to 85°C.
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相关PDF资料 |
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