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参数资料
| 型号： | ICS93V847YG-T |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | 0.173 INCH, MO-153, TSSOP-24 |
| 文件页数： | 5/9页 |
| 文件大小： | 66K |
| 代理商： | ICS93V847YG-T |
5
ICS93V847
0611C—06/18/03
Notes:
1.
Refers to transition on noninverting output in PLL bypass mode.
2.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, were
the cycle (tc) decreases as the frequency goes up.
3.
Switching characteristics guaranteed for application frequency range.
4.
Static phase offset shifted by design.
Timing Requirements
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
freqop
2.5V+0.2V @ 25
oC
33
233
MHz
Application Frequency
Range
freqApp
2.5V+0.2V @ 25
oC
60
170
MHz
Input clock duty cycle
dtin
40
60
%
CLK stabilization
TSTAB
100
s
Switching Characteristics
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Low-to high level
propagation delay time
tPLH
1
CLK_IN to any output
5.5
ns
High-to low level propagation
delay time
tPHL
1
CLK_IN to any output
5.5
ns
Period jitter
tjit (per)
66/100/125/133/167MHz
-40
40
ps
100 to <170MHz
-100
100
ps
≥170MHz to 233MHz
-120
50
ps
Input clock slew rate
tsl(I)
14
v/ns
Output clock slew rate
tsl(o)
66/100/133/167MHz
1
2
v/ns
Cycle to Cycle Jitter
1
tcyc-tcyc
66/100/125/133/167MHz
60
ps
Phase error
t(phase error)
4
-50
0
50
ps
Output to Output Skew
tskew
40
60
ps
Rise Time, Fall Time
tr, tf
Load = 120
/16pF
650
800
950
ps
tjit(hper)
Half-period jitter
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