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参数资料
| 型号： | ICS94203YFLF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 0.300 INCH, SSOP-56 |
| 文件页数： | 18/18页 |
| 文件大小： | 183K |
| 代理商： | ICS94203YFLF-T |
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ICS94203
Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group divider ratio
programmed into bytes 16-20 could be unstable. Step 3 & 7 assure the correct spread and gear ratio.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or too slow.
Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz).
4. Users can also utilize software utility provided to program VCO frequency from ICS Application Engineering.
5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spreadamount desired. See
Application note for software support.
Byte 16: Spread Sectrum Control Register
Byte 17: Spread Spectrum Control Register
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Byte 18: Output Dividers Control Register
Byte 19: Output Dividers Control Register
Note: Changing bits in these registers results in frequency
divider ratio changes. Incorrect configuration of
group gear ratio can cause system malfunction.
Note: Changing bits in these registers results in frequency
divider ratio changes. Incorrect configuration of
group gear ratio can cause system malfunction.
Notes:
1. PWD = Power on Default
2. The power on default for byte 16-20 depends on the harware (latch inputs FS[0:4]) or IIC (Byte 0 bit [1:7]) setting. Be sure to read
back and re-write the values of these 5 registers when VCO frequency change is desired for the first pass.
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相关PDF资料 |
PDF描述 |
|---|---|
| ICS94209YFLF-T | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS94210YF-PPP-T-LF | 166.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS94210YF-PPP-T-LF | 166.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS94210YF-T | 166.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS94210YFLF-T | 166.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS94203YF-T | 制造商:ICS 制造商全称:ICS 功能描述:Programmable System Frequency Generator for PII/III⑩ |
| ICS94206 | 制造商:ICS 制造商全称:ICS 功能描述:Programmable System Frequency Generator for PII/III⑩ |
| ICS94206YF-T | 制造商:ICS 制造商全称:ICS 功能描述:Programmable System Frequency Generator for PII/III⑩ |
| ICS94209 | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Frequency Generator & Integrated Buffers for Pentium III Processor |
| ICS94209YF-T | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Frequency Generator & Integrated Buffers for Pentium III Processor |
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