- 您现在的位置：买卖IC网 > PDF目录296205 > ICS950805YF-T (INTEGRATED DEVICE TECHNOLOGY INC) 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 PDF资料下载
参数资料
| 型号： | ICS950805YF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | XO, clock |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 0.300 INCH, MO-118, SSOP-56 |
| 文件页数： | 15/20页 |
| 文件大小： | 180K |
| 代理商： | ICS950805YF-T |
4
ICS950805
0649H—02/25/05
Byte 0: Control Register
Byte 1: Control Register
t
i
B#
n
i
Pe
m
a
ND
W
P
2
e
p
y
T
1
n
o
i
t
p
i
r
c
s
e
D
0
t
i
B4
50
S
FX
R
n
o
d
e
l
p
m
a
s
n
i
p
0
S
F
f
o
e
u
l
a
v
e
h
t
s
t
c
e
l
f
e
R
p
u
r
e
w
o
p
1
t
i
B5
51
S
FX
R
n
o
d
e
l
p
m
a
s
n
i
p
1
S
F
f
o
e
u
l
a
v
e
h
t
s
t
c
e
l
f
e
R
p
u
r
e
w
o
p
2
t
i
B0
42
S
FX
R
n
o
d
e
l
p
m
a
s
n
i
p
2
S
F
f
o
e
u
l
a
v
e
h
t
s
t
c
e
l
f
e
R
p
u
r
e
w
o
p
3
t
i
B4
3#
P
O
T
S
_
I
C
P
3
XR
f
o
e
u
l
a
v
e
h
t
s
t
c
e
l
f
e
R
:
e
d
o
m
e
r
a
w
d
r
a
H
D
W
P
n
o
d
e
l
p
m
a
s
n
i
p
#
P
O
T
S
_
I
C
P
1W
R
:
e
d
o
m
e
r
a
w
t
f
o
S
d
e
p
o
t
s
K
L
C
I
C
P
=
0
d
e
p
o
t
s
t
o
n
K
L
C
I
C
P
=
1
4
t
i
B3
5#
P
O
T
S
_
U
P
CX
R
l
a
n
r
e
t
x
e
h
t
f
o
e
u
l
a
v
t
n
e
r
u
c
e
h
t
s
t
c
e
l
f
e
R
n
i
p
#
P
O
T
S
_
U
P
C
5
t
i
B5
3H
C
V
/
1
_
6
V
30
W
R
z
H
M
8
4
/
z
H
M
6
t
c
e
l
e
S
H
C
V
z
H
M
8
4
=
1
,
z
H
M
6
=
0
6
t
i
B-
)
0
:
2
(
T
_
U
P
C0
l
e
v
e
l
t
u
p
t
u
o
s
l
o
r
t
n
o
c
e
d
o
m
n
w
o
d
r
e
w
o
p
n
I
h
g
i
h
p
o
t
s
=
0
w
o
l
p
o
t
s
=
1
7
t
i
B-
d
e
l
b
a
n
E
d
a
e
r
p
S0
W
Rn
O
d
a
e
r
p
S
=
1
,
f
O
d
a
e
r
p
S
=
0
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways.
Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert
PCI_STOP functionality via I
2C Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the I
2C Byte 0 Bit3. In Software mode it is not allowed to pull the
external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped
PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it
is not allowed to mix these modes.
In Hardware mode the I
2C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip
is in PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I
2C Byte 0 Bit 3 = 0)].
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
t
i
B#
n
i
Pe
m
a
ND
W
P
2
e
p
y
T
1
n
o
i
t
p
i
r
c
s
e
D
0
t
i
B1
5
,
2
5
0
T
K
L
C
U
P
C
0
C
K
L
C
U
P
C
1W
Rd
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
4
1
t
i
B8
4
,
9
4
1
T
K
L
C
U
P
C
1
C
K
L
C
U
P
C
1W
Rd
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
4
2
t
i
B4
4
,
5
4
2
T
K
L
C
U
P
C
2
C
K
L
C
U
P
C
1W
Rd
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
4
3
t
i
B1
5
,
2
5
0
T
K
L
C
U
P
C
0
C
K
L
C
U
P
C
0W
R
n
o
i
t
r
e
s
a
h
t
i
w
0
C
/
0
T
K
L
C
U
P
C
f
o
l
o
r
t
n
o
c
w
o
ll
A
e
r
F
=
1
g
n
i
n
u
r
e
r
f
t
o
N
=
0
#
P
O
T
S
_
U
P
C
f
o
g
n
i
n
u
r
4
t
i
B8
4
,
9
4
1
T
K
L
C
U
P
C
1
C
K
L
C
U
P
C
0W
R
n
o
i
t
r
e
s
a
h
t
i
w
1
C
/
1
T
K
L
C
U
P
C
f
o
l
o
r
t
n
o
c
w
o
ll
A
e
r
F
=
1
g
n
i
n
u
r
e
r
f
t
o
N
=
0
#
P
O
T
S
_
U
P
C
f
o
g
n
i
n
u
r
5
t
i
B4
4
,
5
4
2
T
K
L
C
U
P
C
2
C
K
L
C
U
P
C
0W
R
n
o
i
t
r
e
s
a
h
t
i
w
2
C
/
2
T
K
L
C
U
P
C
f
o
l
o
r
t
n
o
c
w
o
ll
A
e
r
F
=
1
g
n
i
n
u
r
e
r
f
t
o
N
=
0
#
P
O
T
S
_
U
P
C
f
o
g
n
i
n
u
r
6
t
i
B-
-
0
-
)
d
e
v
r
e
s
e
R
(
7
t
i
B3
40
L
E
S
T
L
U
MX
R
0
L
E
S
T
L
U
M
f
o
e
u
l
a
v
t
n
e
r
u
c
e
h
t
s
t
c
e
l
f
e
R
相关PDF资料 |
PDF描述 |
|---|---|
| ICS950805YFLF-T | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| ICS950905YFLFT | 200.4 MHz, OTHER CLOCK GENERATOR, PDSO48 |
| ICS951704YFLFT | 166 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICT-163-SP122-TG30 | DIP16, IC SOCKET |
| ICT-083-S-TG30 | DIP8, IC SOCKET |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS950810 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator with 200MHz Differential CPU Clocks |
| ICS950810CFLF | 功能描述:IC FREQ GEN 200MHZ CLK 56-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| ICS950810CFLFT | 功能描述:IC FREQ GEN 200MHZ CLK 56-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ICS950810CG | 制造商:INT_CIR_SYS 功能描述: |
| ICS950810CGLF | 功能描述:IC FREQ GEN 200MHZ CLK 56-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
发布紧急采购，3分钟左右您将得到回复。