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参数资料
| 型号： | ICS950805YF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | XO, clock |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 0.300 INCH, MO-118, SSOP-56 |
| 文件页数： | 8/20页 |
| 文件大小： | 180K |
| 代理商： | ICS950805YF-T |
16
ICS950805
0649H—02/25/05
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP#
CPUT
CPUC
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
#
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PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will
latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized
by the next rising edge.
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2C configuration to be stoppable
via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling
as shown. The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the
output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC
signal will not be driven.
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