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参数资料
| 型号： | ICS950805YF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | XO, clock |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 0.300 INCH, MO-118, SSOP-56 |
| 文件页数： | 7/20页 |
| 文件大小： | 180K |
| 代理商： | ICS950805YF-T |
15
ICS950805
0649H—02/25/05
Normal operation transition to Suspend State S1 Entry sequence of events:
1. Power-Down (PD#) pin is taken from a high to low to start into S1 Suspend state with digital filtering of the
transition in the clock circuit.
2. The first clocks to be forced to a Stop Low power down condition are the PCI buffer output clocks after a full
clock cycle. If the PCI_Stop# is low, then the free-running PCI clocks (for PCI and APIC signals) are the
remaining PCI buffer clocks stopped.
3. Immediately after the PCI clocks have been stopped the 66Buf_0:2 clocks are stopped low after the next
high to low transition. It will always be a sequence of PCI stopping, THEN the 66Buf clocks.
4. Following the two buffer output clocks being stopped (PCI then 66.6Buffer outputs), the remaining clocks
within a short delay will transition to a stopped power-down state. The first of these driven clocks that
transition to a stopped state are all of the CPU PLL clocks: the CPU and the driven 3V66 clocks.
5. After the CPU PLL clocks are stopped, the 48 MHz clocks (USB, DOT clocks) will stop low, then the REF
clock 14.318 MHz clock will stop low.
6. After the clocks have all been stopped, the internal PLL stages and the Crystal oscillator will all be driven to
a low power stopped condition.
7. As a note to power management calculations, please be aware that the CPU design requires that in the
Power-Down (S1 mode) the CPU outputs have a differential bias voltage driving the differential input stage of
the CPU in this S1 state. For this PD condition of the clock generator, the IDD_PD is running around 30 to
45 mA from having the Iref running (5 mA), the output multiplier bias generator at a 2X condition and the
output current source outputs are running at a 2xIref bias level (for approx 10 mA each CPU output). This
results in a higher level of Clock generator IDD_PD than in prior generations of clocks due to the CPU output
differential requirements.
Suspend State S1 Exit transition to normal operation sequence of events:
1. Power-Down (PD#) pin is taken from Low to High with digital filtering of the transition in the clock circuit to
return to normal running operation.
2. The Crystal Oscillator and the two PLL stages are released from PD to start-up to normal operation. No
clocks will operate until the Lock detect circuitry verifies the PLL has reached stable final frequency (the
same as normal initial power-up).
3. The CPU PLL clocks (differential CPU outputs and the driven 3V66_(0:1) clocks are operating first as soon
as the Lock detect releases the clocks.
With the release of these clocks, the single 66Buf_1 buffer driven
output (at pin 22) is also released from the PD stopped state (but NOT the other 66Buf0,2 and not the PCI
outputs). This allows the GMCH chipset 66.6 MHz DLL stage to start operating and have an operating
feedback path before the other buffer outputs are released. This change is why the requirement is made that
pin 22 be the connection from the clock to the GMCH chipset.
Note that along with the 66Buf_0,2 and the
PCI clocks, the 48 MHz and REF (14.318 MHz) clocks are also NOT released at this point.
4. A delay is built into the clock generator that allows the CPU, driven 3V66_0,1 and the single buffer clock
66Buf_1 (at pin 22) to operate before other clocks are released. This delay is larger than 30 uS and shorter
than 400 uS, and after this the other clocks are staged for a sequential release.
5. The initial clocks released after the delay are the 66Buf_0, 2 outputs.
6. After the 66Buf_0,2 clocks are released, then the PCI clocks are released.
7. It will always be the sequence of 66_1 (pin 22) released with the CPU clocks, then after the delay the
remaining 66Buf_0,2 first, THEN the PCI clocks.
8. Following the 66Buf_0,2 clocks, the 48 MHz (DOT and USB clocks) and the REF (14.318MHz) clocks are
released.
9. Note, the initial power-up time is the same as this PD release, the PLL will power-up and the outputs will be
running within a 3 ms time point.
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