参数资料
型号: ICS951402AGLF
厂商: IDT, Integrated Device Technology Inc
文件页数: 14/23页
文件大小: 0K
描述: IC TIMING CTRL HUB P4 48-TSSOP
标准包装: 39
系列: TCH™
类型: 时钟/频率发生器,多路复用器
PLL:
主要目的: Intel CPU,Timing Control Hub?
输入: 晶体
输出: 时钟
电路数: 1
比率 - 输入:输出: 1:19
差分 - 输入:输出: 无/是
频率 - 最大: 210MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-TFSOP(0.240",6.10mm 宽)
供应商设备封装: 48-TSSOP
包装: 管件
其它名称: 951402AGLF
21
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their
next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP#
CPUT
CPUC
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
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