参数资料
型号: ICS951402YFLF-T
英文描述: Programmable Timing Control Hub for P4 processor
中文描述: 可编程定时控制中心的P4处理器
文件页数: 13/23页
文件大小: 303K
代理商: ICS951402YFLF-T
13
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
Table 4:
Skew Specification on Output Mode
Bit3
Bit2
Bit1
Bit0
Skew in ps
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
500
750
1000
1250
I
2
C Table
: Group Skew Control Register
Byte 19
Pin #
Name
Control
Function
Reserved
Reserved
Reserved
Reserved
AGP
Skew Control
Reserved
Reserved
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
AGPSkw3
AGPSkw2
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
See 2-bit Skew
Control at table 4
-
-
-
-
I
2
C Table
: Group Skew Control Register
Byte 20
Pin #
Name
Control
Function
PCI_F [1:0]
Skew Control
Reserved
Reserved
PCI [5:0]
Skew Control
Reserved
Reserved
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
PCISkw3
PCISkw2
Reserved
Reserved
PCISkw1
PCISkw0
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
See 2-bit Skew
Control at table 4
-
-
See 2-bit Skew
Control at table 4
-
-
-
-
-
-
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