参数资料
型号: ICS951402YFLF-T
英文描述: Programmable Timing Control Hub for P4 processor
中文描述: 可编程定时控制中心的P4处理器
文件页数: 18/23页
文件大小: 303K
代理商: ICS951402YFLF-T
18
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
T
A
= 0 - 70C; VDD=3.3V +/-5%; C
L
= 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
Output Frequency
F
O1
Output Impedance
R
DSP11
Output High Voltage
V
OH1
Output Low Voltage
V
OL1
CONDITIONS
MIN
TYP
48
48
MAX
UNITS
MHz
W
V
V
V
O
= V
DD
*(0.5)
I
OH
= -1 mA
I
OL
= 1 mA
20
2.4
60
0.4
Output High Current
I
OH1
V
OH@MIN
= 1.0 V, V
OH@MAX
=
3.135 V
V
OL @MIN
= 1.95 V, V
OL @MAX
=
0.4 V
V
OL
= 0.4 V, V
OH
= 2.4 V
V
OH
= 2.4 V, V
OL
= 0.4 V
V
OL
= 0.4 V, V
OH
= 2.4 V
V
OH
= 2.4 V, V
OL
= 0.4 V
V
T
= 1.5 V
V
T
= 1.5 V
V
T
= 1.5 V
V
T
= 1.5 V (0 OR 180 degrees)
V
T
= 1.5 V
-29
-23
mA
Output Low Current
I
OL1
29
27
mA
48DOT Rise Time
48DOT Fall Time
VCH 48 USB Rise Time
VCH 48 USB Fall Time
48 DOT Duty Cycle
VCH 48 USB Duty Cycle
48 DOT Jitter
USB to DOT Skew
VCH Jitter
1
Guaranteed by design, not 100% tested in production.
t
r11
t
f11
t
r11
t
f11
d
t11
d
t11
0.5
0.5
1
1
45
45
0.6
0.8
1.2
1.3
52.8
53.5
183
0.43
223
1
1
2
2
ns
ns
ns
ns
%
%
ps
ns
ps
55
55
350
1
350
t
jcyc-cyc1
t
sk11
t
jcyc-cyc1
Electrical Characteristics - SDRAM
T
A
= 0 - 70C; V
DD
=V
DDL
3.3 V +/-5%; C
L
= 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Impedance
R
DSP2A1
Output Impedance
R
DSN2A1
Output High Voltage
V
OH2A
Output Low Voltage
V
OL2A
Output High Current
I
OH2A
Output Low Current
I
OL2A
Rise Time
t
r2A1
Fall Time
t
f2A1
Duty Cycle
d
t2A1
Jitter
1
t
cyc-cyc
1
Guaranteed by design, not 100% tested in production.
CONDITIONS
MIN TYP MAX UNITS
10
10
2.4
V
O
= V
DD
*(0.5)
V
O
= V
DD
*(0.5)
I
OH
= -28 mA
I
OL
= 19 mA
V
OH
= 2.0 V
V
OL
= 0.8 V
V
OL
= 0.4 V, V
OH
= 2.4 V
V
OH
= 2.4 V, V
OL
= 0.4 V
V
T
= 1.5 V
V
T
= 1.5 V
20
20
V
V
mA
mA
ns
ns
%
ps
0.4
-42
33
0.5
0.5
45
2.0
2
55
250.0
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