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参数资料
| 型号： | ICS951402YFLF-T |
| 英文描述： | Programmable Timing Control Hub for P4 processor |
| 中文描述： | 可编程定时控制中心的P4处理器 |
| 文件页数： | 9/23页 |
| 文件大小： | 303K |
| 代理商： | ICS951402YFLF-T |
9
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
I
2
C Table:
Watchdog Timer Register
Byte 9
Pin #
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
Control Function Type
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
1
0
0
0
0
These bits represent
X*293ms the
watchdog timer will
wait before it goes to
alarm mode. Default
is 16 X 293ms =
4
.688
seconds
I
2
C Table
: WD Timer Control Register
Byte 10
Pin #
Name
Control
Function
M/
N Programming
Enable
Watchdog Enable
Type
0
1
PWD
Bit 7
-
M/NEN
RW
Latched
Inputs
Disable
IIC Prog.
B (11:17)
Enable
0
Bit 6
-
WDEN
RW
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note:
If Byte4 bit1 = 0 then FS4=0
I
-
-
-
-
-
-
WDStatus
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
WD Status Control
RW
RW
RW
RW
RW
RW
OFF
-
-
-
-
-
ON
0
1
0
0
0
0
-
-
-
-
-
Writing to
these bit will
configure the safe
frequency as Byte 0 Bit
(6:0
)
2
C Table:
VCO Frequency Control Register
Byte 11
Pin #
Name
Control
Function
N Divider Bit 8
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
N Div8
M Div6
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
The decimal
representation of M
Div (6:0) is equal to
reference divider
value. Default at
power up = latch-in
or Byte 0 Rom table.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS951402YGLF-T | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Timing Control Hub for P4 processor |
| ICS951403 | 制造商:ICS 制造商全称:ICS 功能描述:AMD-K7 System Clock Chip |
| ICS951403YFLF-T | 制造商:ICS 制造商全称:ICS 功能描述:AMD-K7 System Clock Chip |
| ICS951403YGLF-T | 制造商:ICS 制造商全称:ICS 功能描述:AMD-K7 System Clock Chip |
| ICS951411 | 制造商:ICS 制造商全称:ICS 功能描述:System Clock Chip for ATI RS400 P4TM-based Systems |
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