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参数资料
| 型号： | ICS952623YFT |
| 英文描述： | Programmable Timing Control Hub for Next Gen P4 processor |
| 中文描述： | 可编程定时控制中心，为下一代P4处理器 |
| 文件页数： | 3/27页 |
| 文件大小： | 329K |
| 代理商： | ICS952623YFT |
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3
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
0758—02/08/05
Pin Description (Continued)
PIN
#
PIN NAME
PIN TYPE
DESCRIPTION
29
3V66_4/VCH
OUT
66.66MHz clock output for AGP support. AGP-PCI should be
aligned with a skew window tolerance of 500ps.
VCH is 48MHz clock output for video controller hub.
Data pin for I2C circuitry 5V tolerant
48MHz clock output.
48MHz clock output.
Ground pin.
Power for 48MHz output buffers and fixed PLL core.
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
Power supply for SRC clocks, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
"Complementary" clocks of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
"True" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
"Complementary" clocks of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
"True" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
Ground pin.
"Complementary" clocks of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
"True" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Stops all PCICLKs and SRC pair besides the PCICLK_F clocks at
logic 0 level, when input low. PCI and SRC clocks can be set to
Free_Running through I2C. Internal pull-up of 150K nominal.
Stops all CPUCLK besides the free running clocks. Internal pull-up
of 150K nominal
Frequency select pin, see Frequency table for functionality
IREF establishes the reference current for the CPUCLK pairs. A
fixed precision resistor tied to ground is required to establish the
appropriate current.
Ground pin.
Ground pin for core.
3.3V power for the PLL core.
Frequency select pin, see Frequency table for functionality
30
31
32
33
34
SDATA
48MHz_USB
48MHz_DOT
GND
VDD48
I/O
OUT
OUT
PWR
PWR
35
Vtt_PWRGD#
IN
36
VDD
PWR
37
SRCCLKC
OUT
38
SRCCLKT
OUT
39
GND
PWR
40
CPUCLKC0
OUT
41
CPUCLKT0
OUT
42
VDDCPU
PWR
43
CPUCLKC1
OUT
44
CPUCLKT1
OUT
45
GND
PWR
46
CPUCLKC2
OUT
47
CPUCLKT2
OUT
48
VDDCPU
PWR
49
PCI_STOP#
IN
50
CPU_STOP#
IN
51
FS_A
IN
52
IREF
OUT
53
54
55
56
GND
GNDA
VDDA
FS_B
PWR
PWR
PWR
IN
相关PDF资料 |
PDF描述 |
|---|---|
| ICS952623YGT | Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952623 | Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952623YFT | Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952623YGT | Programmable Timing Control Hub for Next Gen P4 processor |
| ICS95V847 | 2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS952623YGT | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952702 | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Timing Control Hub for K7 System |
| ICS952702YFLF-T | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Timing Control Hub for K7 System |
| ICS952703 | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Timing Control Hub for K7 System |
| ICS952703BF | 功能描述:IC TIMING CTRL HUB K7 48-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:TCH™ 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
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