参数资料
型号: ICS952624YFLFT
元件分类: 时钟产生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封装: MO-118, SSOP-48
文件页数: 10/17页
文件大小: 118K
代理商: ICS952624YFLFT
2
Integrated
Circuit
Systems, Inc.
ICS952624
0768B—08/06/03
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
FS_A/REF1
I/O
FS_A latched input for frequency select
Reference output, 14.318Hz
2
FS_B/REF0
I/O
FS_B latched input for frequency select
Reference output, 14.318Hz
3
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
4X1
IN
Crystal input, Nominally 14.318MHz.
5
X2
OUT
Crystal output, Nominally 14.318MHz
6
GND
PWR
Ground pin.
7
PCICLK_F0
OUT
Free running PCI clock not affected by PCI_STOP# .
8
PCICLK_F1
OUT
Free running PCI clock not affected by PCI_STOP# .
9
PCICLK_F2
OUT
Free running PCI clock not affected by PCI_STOP# .
10
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
11
GND
PWR
Ground pin.
12
PCICLK0
OUT
PCI clock output.
13
PCICLK1
OUT
PCI clock output.
14
PCICLK2
OUT
PCI clock output.
15
PCICLK3
OUT
PCI clock output.
16
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
17
GND
PWR
Ground pin.
18
PCICLK4
OUT
PCI clock output.
19
PCICLK5
OUT
PCI clock output.
20
PD#
IN
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 1.8ms.
21
48MHz_DOT
OUT
48.008MHz Dot clock output
22
48MHz_USB
OUT
48.008MHz USB clock output
23
GND
PWR
Ground pin.
24
VDD48
PWR
Power for 48MHz output buffers and fixed PLL core.
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