参数资料
型号: ICS952624YFLFT
元件分类: 时钟产生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封装: MO-118, SSOP-48
文件页数: 4/17页
文件大小: 118K
代理商: ICS952624YFLFT
12
Integrated
Circuit
Systems, Inc.
ICS952624
0768B—08/06/03
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
48MHz_USB
2x output drive
0=2x drive
RW
2x drive
1xdrive
1
Bit 6
48MHz_USB
Output Control
RW
Disable
Enable
1
Bit 5
RESERVED
-
X
Bit 4
RESERVED
-
X
Bit 3
RESERVED
-
X
Bit 2
PCICLK_F2
Output Control
RW
Disable
Enable
1
Bit 1
PCICLK_F1
Output Control
RW
Disable
Enable
1
Bit 0
PCICLK_F0
Output Control
RW
Disable
Enable
1
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
DOT_48MHZ
Output Control
RW
Disable
Enable
1
Bit 6
CPU_T/C_ITP
Output Control
RW
Disable
Enable
1
Bit 5
3V66_3/VHC
Frequency Select
Output Select
RW
3V66
VCH
0
Bit 4
3V66_3/VHC
Output Control
RW
Disable
Enable
1
Bit 3
RESERVED
-
X
Bit 2
3V66_2
Output Control
RW
Disable
Enable
1
Bit 1
3V66_1
Output Control
RW
Disable
Enable
1
Bit 0
3V66_0
Output Control
RW
Disable
Enable
1
I
2C Table: Output Control and Fix Frequecy Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
Test Clock Mode
-
Disable
Enable
0
Bit 6
RESERVED
-
0
Bit 5
CPU *2 Test Clock
FS_A and FS_B
Operation
-
Normal
Test Mode
0
Bit 4
SRC Frequency Select
SRC Frequency
Select
-
100MHz
200MHz
0
Bit 3
Spread Spectrum Type
Down/Center
-
Down
Center
0
Bit 2
Spread Spectrum Mode
Spread Spectrum
Enable
Spread
OFF
Spread
ON
0
Bit 1
REF1
Output Control
RW
Disable
Enable
1
Bit 0
REF0
Output Control
RW
Disable
Enable
1
I
2C Table: Vendor & Revision ID Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
RID3
R
-
0
Bit 6
RID2
R
-
0
Bit 5
RID1
R
-
0
Bit 4
RID0
R
-
0
Bit 3
VID3
R
-
0
Bit 2
VID2
R
-
0
Bit 1
VID1
R
-
0
Bit 0
VID0
R
-
1
RESERVED
VENDOR ID
-
Byte 7
-
REVISION ID
-
Byte 6
Byte 5
Byte 4
RESERVED
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