参数资料
型号: ICS952702YFLFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 222 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封装: LEAD FREE, MO-118, SSOP-48
文件页数: 10/17页
文件大小: 149K
代理商: ICS952702YFLFT
2
Integrated
Circuit
Systems, Inc.
ICS952702
0795D—05/06/05
The ICS952702 is a two chip clock solution for desktop designs using SIS 746 style chipsets. When used with a zero delay
buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks signals
for such a system.
The ICS952702 is part of a whole new line of ICS clock generators and buffers called TCH (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I
2C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
General Description
Block Diagram
Power Groups
PLL2
Frequency
Dividers
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
ZCLK (1:0)
X1
X2
XTAL
CPU_STOP#
PCI_STOP#
SCLK
SEL24_48MHZ
SEL12_48
PD#
FS (4:0)
SDATA
Control
Logic
PCICLK (5:0)
AGPCLK (1:0)
12_48MHZ
24_48MHZ
REF (2:0)
CPUCLKODC0
CPUCLKODT (1:0)
RESET#
IOAPIC (1:0)
PCICLKF (1:0)
VDD
GND
1
5
REF output, Xtal
11
8
Hyper ZCLK output
28
25
24/48MHz fixed, Fixed PLL (Fix1)
13,19
18,24
PCICLK output
29
32
AGP output
48
45
IOAPIC output
38
41
CPU_T/C output
36
37
CPU PLL, CPU MCLK
Pin Number
Description
相关PDF资料
PDF描述
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