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参数资料
| 型号： | ICS952702YFLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 222 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | LEAD FREE, MO-118, SSOP-48 |
| 文件页数： | 11/17页 |
| 文件大小： | 149K |
| 代理商： | ICS952702YFLFT |
3
Integrated
Circuit
Systems, Inc.
ICS952702
0795D—05/06/05
Pin Description
PIN #
PIN NAME
PIN
TYPE
DESCRIPTION
1
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
2
**FS0/REF0
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
3
**FS1/REF1
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
4
**FS4/REF2
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
5
GNDREF
PWR
Ground pin for the REF outputs.
6
X1
IN
Crystal input, Nominally 14.318MHz.
7
X2
OUT
Crystal output, Nominally 14.318MHz
8
GNDZ
PWR
Ground pin for the ZCLK outputs
9ZCLK0
OUT
3.3V Hyperzip clock output.
10
ZCLK1
OUT
3.3V Hyperzip clock output.
11
VDDZ
PWR
Power supply for ZCLK clocks, nominal 3.3V
12
*PCI_STOP#
IN
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low.
13
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
14
**FS2/PCICLK_F0
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
15
*FS3/PCICLK_F1
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
16
PCICLK0
OUT
PCI clock output.
17
PCICLK1
OUT
PCI clock output.
18
GNDPCI
PWR
Ground pin for the PCI outputs
19
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
20
PCICLK2
OUT
PCI clock output.
21
PCICLK3
OUT
PCI clock output.
22
PCICLK4
OUT
PCI clock output.
23
PCICLK5
OUT
PCI clock output.
24
GNDPCI
PWR
Ground pin for the PCI outputs
25
GND48
PWR
Ground pin for the 48MHz outputs
26
24_48MHz/SEL24#_48MHz**
I/O
Selectable 24 or 48MHz clock output / Latched select input for 24/48MHz output. 0=24MHz,
1 = 48MHz.
27
12_48MHz/SEL12#_48MHz*
I/O
Selectable 12 or 48MHz clock output / Latched select input for 12/48MHz output. 0=12MHz,
1 = 48MHz.
28
AVDD48
PWR
Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
29
VDDAGP
PWR
Power supply for AGP clocks, nominal 3.3V
30
AGPCLK1
OUT
AGP clock output
31
AGPCLK0
OUT
AGP clock output
32
GNDAGP
PWR
Ground pin for the AGP outputs
33
PD#*
IN
Asynchronous active low input pin used to power down the device into a low power state. The
internal clocks are disabled and the VCO and the crystal are stopped. The latency of the
power down will not be greater than 1.8ms.
34
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
35
SCLK
IN
Clock pin of I2C circuitry 5V tolerant
36
AVDD
PWR
3.3V Analog Power pin for Core PLL
37
AGND
PWR
Analog Ground pin for Core PLL
38
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
39
CPUCLKODC0
OUT
"Complememtary" clocks of differential pair CPU outputs. These open drain outputs need an
external 1.5V pull-up.
40
CPUCLKODT0
OUT
True clock of differential pair CPU outputs. These open drain outputs need an external 1.5V
pull-up.
41
GNDCPU
PWR
Ground pin for the CPU outputs
42
RESET#
OUT
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
This signal is active low.
43
CPUCLKODT1
OUT
True clock of differential pair CPU outputs. These open drain outputs need an external 1.5V
pull-up.
44
CPU_STOP#*
IN
Stops all CPUCLK besides the free running clocks
45
GNDAPIC
PWR
Ground pin for the IOAPIC outputs.
46
IOAPIC0
OUT
IOAPIC clock outputs, norminal 2.5V.
47
IOAPIC1
OUT
IOAPIC clock outputs, norminal 2.5V.
48
VDDLAPIC
PWR
Power pin for the IOAPIC outputs. 2.5V.
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
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