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参数资料
| 型号： | ICS954321YG-T |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64 |
| 封装： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-64 |
| 文件页数： | 11/18页 |
| 文件大小： | 221K |
| 代理商： | ICS954321YG-T |
2
Integrated
Circuit
Systems, Inc.
ICS954321
1078A—08/02/05
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
2
GND
PWR
Ground pin.
3
PCICLK1
OUT
PCI clock output.
4
PCICLK2
OUT
PCI clock output.
5
*SEL_LCDCLK#/PCICLK3
I/O
Latched input select for LCD_ss/ SRCCLK output frequency:
0 = LCD,
1 = SRCCLK/ 3.3V free-running PCI clock output.
6
ITP_EN/PCICLK_F0
I/O
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
7*OE0#
IN
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
8*OE1#
IN
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
9*OE2#
IN
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
10
Vtt_PwrGd#/PD
IN
Vtt_PwrGd# is an active low input used to determine when latched inputs are
ready to be sampled. PD is an asynchronous active high input pin used to put the
device into a low power state. The internal clocks, PLLs and the crystal oscillator
are stopped.
11
VDD48
PWR
Power pin for the 48MHz output.3.3V
12
FSLA/USB_48MHz
I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output.
3.3V.
13
GND
PWR
Ground pin.
14
DOTT_96MHz
OUT
True clock of differential pair for 96.00MHz DOT clock.
15
DOTC_96MHz
OUT
Complement clock of differential pair for 96.00MHz DOT clock.
16
FSLB/TEST_MODE
IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to
select between Hi-Z and REF/N divider mode while in test mode. Refer to Test
Clarification Table.
17
LCDCLK_SST/SRCCLKT0
OUT
True clock of LCDCLK_SS output / True clock of SRCCLK differential pair.
Selected by SEL_LCDCLK#
18
LCDCLK_SSC/SRCCLKC0
OUT
Complementary clock of LCDCLK_SS output / Complementary clock of SRCCLK
differential pair. Selected by SEL_LCDCLK#
19
SRCCLKT1
OUT
True clock of differential SRC clock pair.
20
SRCCLKC1
OUT
Complement clock of differential push-pull SRC clock pair.
21
VDDSRC
PWR
Supply for SRC clocks, 3.3V nominal
22
SRCCLKT2
OUT
True clock of differential SRC clock pair.
23
SRCCLKC2
OUT
Complement clock of differential SRC clock pair.
24
SRCCLKT3
OUT
True clock of differential SRC clock pair.
25
SRCCLKC3
OUT
Complement clock of differential SRC clock pair.
26
SRCCLKT4
OUT
True clock of differential SRC clock pair.
27
SRCCLKC4
OUT
Complement clock of differential SRC clock pair.
28
VDDSRC
PWR
Supply for SRC clocks, 3.3V nominal
29
GND
PWR
Ground pin.
30
SRCCLKT5
OUT
True clock of differential SRC clock pair.
31
SRCCLKC5
OUT
Complement clock of differential SRC clock pair.
32
*OE3#
IN
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
Note: Pins 5, 7, 8, 9, 32, 33, and 34 have internal pull-up resistors
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