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| 型号： | ICS9DB106YG-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封装： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28 |
| 文件页数： | 10/14页 |
| 文件大小： | 164K |
| 代理商： | ICS9DB106YG-T |
5
Integrated
Circuit
Systems, Inc.
ICS9DB106
0833C—08/17/06
Electrical Characteristics - PCIEX 0.7V Current Mode Differential Outputs
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2
, RP=49.9, ΙREF = 475
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Current Source Output
Impedance
Zo
1
VO = Vx
3000
1
Voltage High
VHigh
660
850
1,3
Voltage Low
VLow
-150
150
1,3
Max Voltage
Vovs
1150
1,3
Min VoltageVuds
-300
1,3
Crossing Voltage (abs)
Vcross(abs)
250
550
mV
1,3
Crossing Voltage (var)
d-Vcross
Variation of crossing over all
edges
140
mV
1,3
Long Accuracy
ppmsee Tperiod min-max values
0
ppm1,2
100.00MHz nominal
9.9970
10.0030
ns
2
100.00MHz spread
9.9970
10.0533
ns
2
Absolute min period
Tabsmin
100.00MHz nominal/spread
9.8720
ns
1,2
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
700
ps
1
Fall Time
tf
VOH = 0.525V VOL = 0.175V
175
700
ps
1
Rise Time Variation
d-tr
125
ps
1
Fall Time Variation
d-tf
125
ps
1
tpd
PLL Mode.
100
150
ps
1
tpdbyp
Bypass mode
3.2
3.7
ns
1
Duty Cycle
dt3
Measurement from differential
wavefrom
45
55
%
1
Output-to-Output Skew
tsk3
VT = 50%
45
ps
1
PLL mode,
Measurement from differential
wavefrom
35
ps
1
BYPASS mode as additive jitter
35
ps
1
1Guaranteed by design and characterization, not 100% tested in production.
3I
REF = VDD/(3xRR). For RR = 475
(1%), I
REF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50
.
Statistical measurement on single
ended signal using oscilloscope
math function.
mV
Measurement on single ended
signal using absolute value.
mV
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock
complies with CK409/CK410 accuracy requirements
Jitter, Cycle to cycle
tjcyc-cyc
Average period
Tperiod
Input to Output Delay
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