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参数资料
| 型号： | ICSSSTUAF32866C |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| 中文描述： | 25位可配置注册缓冲内存 |
| 文件页数： | 7/31页 |
| 文件大小： | 562K |
| 代理商： | ICSSSTUAF32866C |
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ICSSSTUAF32866C
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
7
ICSSSTUAF32866C
7100/9
Parity and Standby Function Table
Inputs
1
CLK
Outputs
PPO
RESET
DCS
CSR
CLK
Σ
of Inputs = H
(D1 - D25)
PAR_IN
2
QERR
3
H
L
X
↑
↑
↑
↑
↑
↑
↑
↑
↑
↓
↓
↓
↓
↓
↓
↓
↓
↓
Even
L
L
H
H
L
X
Odd
L
H
L
H
L
X
Even
H
H
L
H
L
X
Odd
H
L
H
H
X
L
Even
L
L
H
H
X
L
Odd
L
H
L
H
X
L
Even
H
H
L
H
X
L
Odd
H
L
H
H
H
H
X
X
PPO
0
PPO
0
L
QERR
0
QERR
0
H
H
X
X
L or H
L or H
X
X
L
X or
Floating
X or
Floating
X or
Floating
X or
Floating
X or Floating
X or Floating
1
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑
= LOW to HIGH
↓
= HIGH to LOW
Data Inputs = D2, D3, D5, D6, D8 - D25 when C0 = 0 and C1 = 0.
Data Inputs = D2, D3, D5, D6, D8 - D14 when C0 = 0 and C1 = 1.
Data Inputs = D1 - D6, D8 - D10, D12, D13 when C0 = 1 and C1 = 1.
PAR_IN arrives one clock cycle after the data to which it applies when C0 = 0, and two clock cycles when
C0 = 1.
3
This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If
QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW.
2
相关PDF资料 |
PDF描述 |
|---|---|
| ICSSSTUAF32866CHLFT | 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32868A | 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32868AHLFT | 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAH32865A | 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAH32865AHLFT | 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICSSSTUAF32866CHLFT | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32868A | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32868AHLFT | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32868B | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32868BHLF | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
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