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参数资料
| 型号： | ICSSSTUB32871AHMLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 锁存器 |
| 英文描述： | 32871 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封装： | 5 X 11.50 MM, MO-205, TFBGA-96 |
| 文件页数： | 15/18页 |
| 文件大小： | 199K |
| 代理商： | ICSSSTUB32871AHMLFT |
6
1186G—04/16/07
ICSSSTUB32871A
Parity Functionality Block Diagram
D
21
D
LATCHING AND
RESET FUNCTION
see Note (1)
PTYERR
D
Qn
Dn
PARIN
CLOCK
Q
002aaa417
21
(1) This function holds the error for two
cycles. See functional description and
timing diagram.
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| ICSSSTUF32864AYH-T | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
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| ICSSSTUF32866EHT | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICSSSTUB32871AZLFT | 制造商:ICS 制造商全称:ICS 功能描述:27-Bit Registered Buffer for DDR2 |
| ICSSSTUB32871AZT | 制造商:ICS 制造商全称:ICS 功能描述:27-Bit Registered Buffer for DDR2 |
| ICSSSTUB32872A | 制造商:ICS 制造商全称:ICS 功能描述:28-Bit Registered Buffer for DDR2 |
| ICSSSTUBF32866A | 制造商:ICS 制造商全称:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUBF32866AZ(LF)T | 制造商:ICS 制造商全称:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
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