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参数资料
| 型号： | ICSSSTUB32871AHMLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 锁存器 |
| 英文描述： | 32871 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封装： | 5 X 11.50 MM, MO-205, TFBGA-96 |
| 文件页数： | 4/18页 |
| 文件大小： | 199K |
| 代理商： | ICSSSTUB32871AHMLFT |
12
1186G—04/16/07
ICSSSTUB32871A
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol
Parameter
Measurement
Conditions
MIN
MAX
Units
fmax
Max input clock frequency
410
MHz
tPDM
Propagation delay, single
bit switching
CLK
↑ and CLK↓ to Qn
1.25
1.9
ns
tLH
Low to High propagation
delay
CLK
↑ and CLK↓ to
PTYERR
1.2
3
ns
tHL
High to low propagation
delay
CLK
↑ and CLK↓ to
PTYERR
0.9
3
ns
tPDMSS
Propagation delay
simultaneous switching
CLK
↑ and CLK↓ to Qn
2
ns
tPHL
High to low propagation
delay
RESET ↓ to Qn↓
3ns
tPLH
Low to High propagation
delay
RESET ↓ to PTYERR↑
3ns
1. Guaranteed by design, not 100% tested in production.
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
MAX
fclock
Clock frequency
410
MHz
tW
Pulse duration
1
ns
tACT
Differential inputs active time
10
ns
tINACT
Differential inputs inactive time
15
ns
tS
Data before CLK
↑, CLK↓
0.6
DCS0, DSC1 before CLK↑,
CLK↓, CSR HIGH
0.7
Hold time
DCS, DODT, DCKE and Dn
after CLK
↑, CLK↓
0.6
ns
Hold time
PAR_IN after CLK
↑, CLK↓
0.5
ns
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
4 - CLK/
CLK signal input slew rate of 1V/ns.
SYMBOL
Notes:
tH
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
VDD = 1.8V ±0.1V
UNITS
PARAMETERS
ns
Setup time
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICSSSTUB32871AZLFT | 制造商:ICS 制造商全称:ICS 功能描述:27-Bit Registered Buffer for DDR2 |
| ICSSSTUB32871AZT | 制造商:ICS 制造商全称:ICS 功能描述:27-Bit Registered Buffer for DDR2 |
| ICSSSTUB32872A | 制造商:ICS 制造商全称:ICS 功能描述:28-Bit Registered Buffer for DDR2 |
| ICSSSTUBF32866A | 制造商:ICS 制造商全称:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUBF32866AZ(LF)T | 制造商:ICS 制造商全称:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
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